Methods and systems for managing sets of transactions for replication are provided. A system includes a number of origination nodes forming a source array. A sequence number generator generates sequence numbers based, at least in part, on a time interval during which a transaction is received. A subset manager groups transactions into subsets based, at least in part, on the sequence number.

A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

An image processing apparatus includes: a controller configured to: control a reader to read an image on a reading medium; determine whether a preview image corresponding to the read image is to be displayed on a display, based on a setting value for a setting item, reading-obtained information, or the setting value and the reading-obtained information, in a case where the controller determines that the preview image is to be displayed, control the display to display the preview image, and execute a particular processing based on obtained read-image data in a case where a processing instruction is input after the preview image is displayed; and in a case where the controller determines that the preview image is not to be displayed, execute the particular processing based on the read-image data without displaying the preview image.

An image processing apparatus includes: a controller configured to: control a reader to read an image on a reading medium; determine whether a preview image corresponding to the read image is to be displayed on a display, based on a setting value for a setting item, reading-obtained information, or the setting value and the reading-obtained information, in a case where the controller determines that the preview image is to be displayed, control the display to display the preview image, and execute a particular processing based on obtained read-image data in a case where a processing instruction is input after the preview image is displayed; and in a case where the controller determines that the preview image is not to be displayed, execute the particular processing based on the read-image data without displaying the preview image.

N-way associative cache pools can be implemented in an N-way associative cache. Different cache pools can be indicated by pool values. Different processes running on a computer can use different cache pools. An N-way associative cache circuit can be configured to have one or more stripe mode cache pools that are N-way associative. A cache control circuit can receive a physical address for a memory location and can interpret the physical address as fields including a tag field that contains a tag value and a set field that contains a set value. The physical address can also be used to determine a pool value that identifies one of the stripe mode cache pools. A set of N cache entries in the one of the stripe mode cache pools can be concurrently searched for the tag value. The set of N cache entries is determined using the set value.

Pre-fetching instructions for tasks of an operating system (OS) is provided by calling a task scheduler that determines a load start time for a set of instructions for a particular task corresponding to a task switch condition. The OS calls, and in response to the load start time, a loader entity module that generates a pre-fetch request that loads the set of instructions for the particular task from a non-volatile memory circuit into a random access memory circuit. The OS calls the task scheduler to switch to the particular task.

A task control circuit maintains, in response to task event information, a task information queue that includes task information for a plurality of tasks. Based upon the task information in the task information queue, a future task switch condition is identified as corresponding to a task switch time for a particular task of the plurality of tasks. A load start time is determined for a set of instructions for the particular task. A pre-fetch request is generated to load the set of instructions for the particular task into the memory circuit. The pre-fetch request is forwarded to a hardware loader circuit. In response to the task switch time, a task event trigger is generated for the particular task. The hardware loader circuit is used to load, in response to the pre-fetch request, the set of instructions from a non-volatile memory into the memory circuit.

One or more computing devices, systems, and/or methods are provided. In an example, a method comprises storing a first application image and a second application image in an application image memory, designating the first application image as active, receiving a first address for accessing the application image memory from a processor, modifying the first address based on a first offset between a base starting address of the first application image and a starting physical address of the first application image in the application image memory to generate a second address, and accessing the application image memory using the second address.

One or more computing devices, systems, and/or methods are provided. In an example, a method comprises storing a first application image and a second application image in an application image memory, designating the first application image as active, receiving a first address for accessing the application image memory from a processor, modifying the first address based on a first offset between a base starting address of the first application image and a starting physical address of the first application image in the application image memory to generate a second address, and accessing the application image memory using the second address.