The present disclosure relates to devices and methods for using a banked memory structure with accelerators. The devices and methods may segment and isolate dataflows in datapath and memory of the accelerator. The devices and methods may provide each data channel with its own register memory bank. The devices and methods may use a memory address decoder to place the local variables in the proper memory bank.

Data is stored at a cache portion of a cache memory of a memory sub-system responsive to a request to perform a write operation to write the data. A duplicate copy of the data is stored at a write buffer portion of the cache memory. The cache memory is partitioned into the cache portion and the write buffer portion. An entry that maps a location of the duplicate copy of the data stored at the write buffer portion of the cache memory to a location of the data stored at the cache portion of the cache memory is recorded in a write buffer record.

A memory system of an embodiment includes a nonvolatile memory, a primary cache memory, a secondary cache memory, and a processor. The processor performs address conversion by using logical-to-physical address conversion information relating to data to be addressed in the nonvolatile memory. Based on whether first processing is performed on the nonvolatile memory or second processing is performed on the nonvolatile memory, the processor controls to store whether the logical-to-physical address conversion information relating to the first processing to be in the primary cache memory as cache data or logical-to-physical address conversion information relating to the second processing to be in the secondary cache memory as cache data.

A time period is received from a user over which memory settings of a microservice are to be dynamically managed. Memory settings for the microservice are stored in a configuration file. During the time period, memory utilization of a set of memory regions provided by a process virtual machine for execution of the microservice is monitored. The memory utilization of each memory region is analyzed to identify memory regions that have been over-utilized and memory regions that have been under-utilized. For each memory region identified as being over-utilized or under-utilized, a memory setting in the configuration file and corresponding to an identified memory region is changed. After the change and once the microservice has entered an idle state, a command is generated to restart the microservice so that the changed memory settings can take effect.

A time period is received from a user over which memory settings of a microservice are to be dynamically managed. Memory settings for the microservice are stored in a configuration file. During the time period, memory utilization of a set of memory regions provided by a process virtual machine for execution of the microservice is monitored. The memory utilization of each memory region is analyzed to identify memory regions that have been over-utilized and memory regions that have been under-utilized. For each memory region identified as being over-utilized or under-utilized, a memory setting in the configuration file and corresponding to an identified memory region is changed. After the change and once the microservice has entered an idle state, a command is generated to restart the microservice so that the changed memory settings can take effect.

Disclosed are various embodiments for improving the resiliency and performance of cluster memory. First, a computing device can submit a write request to a byte-addressable chunk of memory stored by a memory host, wherein the byte-addressable chunk of memory is read-only. Then, the computing device can determine that a page-fault occurred in response to the write request. Next, the computing device can copy a page associated with the write request from the byte-addressable chunk of memory to the memory of the computing device. Subsequently, the computing device can free the page from the memory host. Then, the computing device can update a page table entry for the page to refer to a location of the page in the memory of the computing device.

Apparatuses, systems, and techniques to manage memory arrays. In at least one embodiment an application programming interface (API) is performed to disassociate a virtual address indicated by the API from a corresponding physical address.

A method to transfer an artificial intelligence (AI) model includes identifying a plurality of layers of the AI model, the plurality of layers organized in a first ordered list. The method further includes randomizing the plurality of layers by reorganizing the first ordered list into a second ordered list, and transferring the plurality of layers of the AI model to a data processing accelerator in an order defined by the second ordered list.

A method to transfer an artificial intelligence (AI) model includes identifying a plurality of layers of the AI model, the plurality of layers organized in a first ordered list. The method further includes randomizing the plurality of layers by reorganizing the first ordered list into a second ordered list, and transferring the plurality of layers of the AI model to a data processing accelerator in an order defined by the second ordered list.

Power consumption can be reduced by selective memory chip hibernation. For example, a computing device can allocate first data associated with a first processing operation of a user device to a first chip of a dynamic random access memory (DRAM) of the user device. The computing device can allocate second data associated with a second processing operation of the user device to a second chip of the DRAM of the user device. The computing device can determine the first processing operation has been inactive for a predetermined period of time and migrate the first data from the first chip of the DRAM to a storage device of the user device. The computing device can hibernate the first chip of the DRAM while maintaining power to the second chip of the DRAM for continuing to perform the second processing operation.