A user equipment (UE). The UE comprises a memory module, wherein the memory module is one of a subscriber identity module (SIM), a universal integrated circuit card (UICC), a universal subscriber identity module (USIM), or a removable user identity module (R-UIM), wherein clock signals from a second clock component are input to the memory module. The memory module comprises an application stored in a trusted security zone in the second non-transitory memory, that when executed by the second processor in the trusted security zone, wherein the second operating system accesses the second processor to implement instructions for applications in the second operating system, wherein the trusted security zone provides hardware assisted trust, compares a first mobile equipment identifier (MEID) stored in the first non-transitory memory with a second MEID stored in the memory module.

A security agent configured to initiate a security agent component as a hypervisor for a computing device is described herein. The security agent is further configured to determine a subset of memory locations in memory of the computing device to be intercepted. The security agent component may then set intercepts for the determined memory locations. Setting such intercepts may include setting privilege attributes for pages which include the determined memory locations so as to prevent specific operations in association with those memory locations. In response to one of those specific operations, the security agent component may return a false indication of success or allow the operation to enable monitoring of the actor associated with the operation. When an operation affects another memory location associated with one of the pages, the security agent component may temporarily reset the privilege attribute for that page to allow the operation.

A system, method, and apparatus are provided for securely controlling operations of a data processing system by activating a security subsystem to control startup behavior of application subsystems, installing SMR parameters which include an initial authenticity proof for use with an initial verification process for the SMR and calculating an alternate authenticity proof for use with a subsequent verification process for the SMR, and then by subsequently verifying the SMR using the alternate authenticity proof for the subsequent verification process applied to the SMR so that the security subsystem can apply a comprehensive system reaction for the application subsystem based on the SMR verification results.

Techniques for automating quantum circuit debugging are provided that simulate standard debugging behaviors. The technology includes rewriting a source quantum circuit into instrumented circuits based on instrumentation instruction information inserted into software code that corresponds to the source quantum circuit. The instrumented circuits can executed to obtain measurement data corresponding to different state data of qubits within the source quantum circuit. The measurement data can be processed to output generated information corresponding to one or more internal states or processes of a quantum computer associated with the source quantum circuit.

Some examples described relate to securing a memory device of a computing system. For instance, a method may comprise comparing a command for the memory device to each command in a list of commands. The command is accepted when the command matches an authorized command in the list of commands. The accepted command is issued to the memory device.

Provided is a storage device which communicates with a host device and configured to set a secure mode of a plurality of commands different in kind. An operating method of the storage device includes receiving a secure request indicating a protection of a first command and a protection of a second command of the plurality of commands, from the host device; setting a secure mode of the first and second commands, based on the secure request; receiving a first request indicating a request to execute the first command, from the host device; outputting a first response indicating failure of the first command to the host device, based on the first request; receiving a second request indicating a request to execute the second command, from the host device; and outputting a second response indicating failure of the second command to the host device, based on the second request.

A computer device performs operations for managing registry access, including monitoring a user process on the computer device and, in response, establishing a set of registry access rules relevant to the user process. Each registry operation requested by the user process is evaluated and, in response, an appropriate action determined. Such action suitably includes at least one of: blocking the registry operation in relation to a particular key in a registry of the operating system, and enabling access to a particular key in the registry of the operating system to perform the requested registry operation. In particular, the operations may be performed using a registry filter driver in a kernel mode of an operating system of the computer device.

A method is provided. The method is implemented by a secure interface control of a computer that prevents unauthorized accesses to locations in a memory of the computer. The secure interface control determines that a host absolute page is not previously mapped to a virtual page in accordance with securing the host absolute page and a host virtual page is not already mapped to an absolute page in accordance with securing the host absolute page.

A method of protecting a sensitive data sequence in an integrated circuit includes generating a pseudorandom sequence according to a seed sequence; combining the sensitive data sequence with the pseudorandom sequence to generate a protected data sequence; and storing the protected data sequence and the seed sequence. The sensitive data sequence is inaccessible from outside of the integrated circuit.

A system and corresponding method improve a processing system. The system comprises a first learning system coupled to a system controller. The first learning system identifies variations for altering processing of a processing system to meet at least one goal. The system controller applies the variations identified to the processing system. The system further comprises a second learning system coupled to the system controller. The second learning system determines respective effects of the variations identified and applied. The first learning system converges on a given variation of the variations based on the respective effects determined. The given variation enables the at least one goal to be met, improving the processing system, such as by increasing throughput, reducing latency, reducing power consumption, reducing temperature, etc.