A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral configured to communicate with at least one further processor memory mapped peripheral to control the sharing of the data, wherein the memory mapped peripheral includes a sender part including a data request generator configured to output a data request indicator to the further processor module dependent on a data request register write signal from the processor; and an acknowledgement waiting signal generator configured to output an acknowledgement waiting signal to the processor dependent on a data acknowledgement signal from the further processor module, wherein the data request generator data request indicator is further dependent on the data acknowledgement signal and the acknowledgement waiting signal generator acknowledgement waiting signal is further dependent on the acknowledgement waiting register write signal.

An electronic meeting tool and method for communicating arbitrary media content from users at a meeting comprises a node configuration means adapted to operate a display node of a communications network, the display node being coupled to a first display. The node configuration means is adapted to receive user selected arbitrary media content and to control display of the user selected arbitrary media content on the first display. A peripheral device adapted to communicate the user selected arbitrary media content via the communications network is a connection unit comprising a connector adapted to couple to a port of a processing device having a second display, a memory and an operating system, and a transmitter. A program is adapted to obtain user selected arbitrary media content, said program leaving a zero footprint on termination. The user may trigger transfer of said user selected arbitrary media content to said transmitter.

[Problem] To reduce processing load on the CPU driving an OS.

[Solution] This device is provided with a multicore microprocessor unit (21) capable of inter-processor communication, a storage means (22) for storing a file describing device configuration information, and a device interface (23). Threads of the microprocessor unit are separated: a first processor core drives the OS, and meanwhile, a second processor core drives the device driver for controlling the device interface. While sharing the device configuration information by inter-processor communication, a notification driver interface for notifying the operating system kernel of configuration information on the basis of the device configuration information is loaded and the second processor core controls the device connected to the device interface by reading a scenario sequence file into the notification driver.

A bus contention detection circuit includes a delay unit having an input terminal for receiving an output signal of an I/O driver, a duty cycle adjustment unit connected to the delay unit, and a comparison unit having a first input terminal for receiving the output signal, a second terminal for receiving a reference voltage, and an enable terminal for receiving an enable signal of the duty cycle adjustment unit. The enable signal has a rising edge that is delayed relative to a rising edge of the output signal and a falling edge that is aligned with a falling edge of the output signal. The comparison unit compares a voltage level of the output signal with the reference voltage when the enable signal is in a stable voltage state and determine a bus condition in response to a comparison result.

The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a physical layer output signal according to a serializer/deserializer (SerDes) reception signal; an input/output (I/O) circuit operable to generate at least one terminal output signal according to signal variation of at least one terminal; and a processing circuit operable to make the solid state drive control device adapt to one of several interface types in accordance with the physical layer output signal and/or the at least one terminal output signal.

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller’s performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

A system that incorporates the subject disclosure may include, for example, a processor that performs operations including detecting a first depression range of a button that includes an electro-mechanical sensor for detecting the first depression range, comparing the first depression range to a first actuation threshold, and asserting a first actuation state when the first depression range is at or exceeds the first actuation threshold. Additional embodiments are disclosed.

Methods, systems and computer program products are provided for improving performance (e.g., reducing power consumption) of a hardware accelerator (e.g., neural processor) comprising hybrid or analog multiply and accumulate (MAC) processing elements (PEs). Selective variation of the precision of an array of MAC PEs may reduce power consumption of a neural processor. Power may be conserved by dynamically controlling the precision of analog to digital (ADC) output bits for one or more MAC PEs. Dynamic control of ADC output bit precision may be based on precision information determined during training and/or post-training (e.g., quantization) of an artificial intelligence (AI) neural network (NN) model implemented by the neural processor. Precision information may include a range of dynamic precision for each of a plurality of nodes of a computation graph for the AI NN model.

A computer system and method for delivering synchronized metadata for a media to a target device that is associated with a plurality of peripherals.

A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative auxiliary channel pin. At the other end is a micro serial interface connector, wherein multimedia content is transmitted over the cable adaptor and electrical power is supplied over the cable adaptor simultaneously. The cable adaptor has an auxiliary and hot plug detect (HPD) controller utilized to map the auxiliary channel and HPD signals of the packet-based digital display to the micro serial interface ID signal.