A technology is described for converting a time tag in a message. The message can be received from a military standard-1760 (MIL-STD-1760) bus controller. The message can include a time tag in accordance with a first time stamping technique. The time tag in the message can be detected as being in accordance with the first time stamping technique based on contents of the message. A recomputed time tag for the message can be determined in accordance with a second time stamping technique. The message with the recomputed time tag can be transmitted to a Universal Armament Interface (UAI) remote terminal

In accordance with some embodiments, an apparatus that controls device re-configuration for security is provided. The apparatus includes a storage storing a first firmware image for a re-configurable data communication device. In some embodiments, the first firmware image provides one or more operating parameter configurations for the re-configurable data communication device. The apparatus also includes a controller, which is coupled to the storage and the re-configurable data communication device and operable to manage transport of data by the re-configurable data communication device, including obtaining the first firmware image from the storage and loading the first firmware image to the re-configurable data communication device. The apparatus additionally includes a housing at least partially supporting the storage and the controller.

A network teaming system includes one or more subsystems to provide a hardware system integrated teaming assistant (SITA hardware), provide a software system integrated teaming assistant (SITA software) operable with the SITA hardware and provide a feature checking and enablement system (FCE), wherein the FCE determines one or more networking features for members of a team coupled together on a network, and wherein the SITA hardware in combination with the SITA software perform a networking feature for a member of the team which does not have the capability to perform the networking feature.

The present disclosure includes apparatuses and methods related to distributed input/output (I/O) virtualization. A number of embodiments include an apparatus comprising a host computing device, a distributed virtualization controller (DVC) disposed on the host computing device, and a virtualized input/output (I/O) device in communication with the DVC.

An application-classification and peripheral device settings (APDS) system may comprise a categorization subsystem to capture descriptive information about an application, analyze the descriptive information, determine a classification of the application, and assign the application to an application category that includes applications that each have a similar classification. The system may also include a peripheral device configuration subsystem to identify a peripheral device setting from the application category and apply the peripheral device setting to an operating configuration of the application.

An electronic device comprising circuitry configured to detect and read commands of a x-by-wire system (ECU1, ECU2, 25) from a communication bus (FLR) and to use the commands of the x-by-wire system (ECU1, ECU2, 25) as an input for an electronic gaming or simulation device (30).

System and method of using a processor driven master Quad-SPI (QSPI) bus or interface to simultaneously and time-synchronously transmit different streams of data from a FIFO buffer to a plurality of different slave SPI interface peripherals. Here the QSPI interface data ports are configured to simultaneously transmit multiple 1 bit wide streams of different binary data and different chip select commands on an SPI clock cycle synchronized basis. Additional SPI slave peripherals may be controlled by use of additional non-SPI clock synchronized GPIO chip select commands and suitable logic gates. These methods are useful for creating a variety of embedded systems with faster response speeds, such as improved microwave frequency synthesizers with faster frequency changing times.

A network interface card configuration method and a resource management center are provided. According to the method, after obtaining a network interface card allocation request of an operating system that runs in a first CPU core, a resource management center selects, from M physical network interface cards and based on a network parameter of a network service required by the operating system, a target physical network interface card that conforms to the network parameter. Further, the resource management center selects at least one target hardware queue from each target physical network interface card and sends a command message to a network interface card controller. After receiving queue information of the target hardware queue from the network interface card controller, the resource management center send an instruction message to a CPU controller on a CPU board to instruct the CPU controller to construct a virtual network interface card.

The present application discloses an atomization assembly, an electronic cigarette with a limited lifetime and a method of limiting a lifetime of the electronic cigarette. The atomization assembly includes an interface circuit detachably connected with the battery assembly, an atomization circuit and a main circuit. The atomization circuit and the main circuit are both connected with the interface circuit. The main circuit is used to count the puff number according to actual conducting times of the atomization circuit, after electrically communicated with the battery assembly via the interface circuit, so that the electronic cigarette controls the atomizing circuit to be disconnected and stopped from working when the puff number reaches a preset value. A technical effect is achieved that exactly counting the puff number and effectively ensuring the consistency between the available puff number and available amount of tobacco tar.

A device for monitoring a resolver disposed on a rotatable member is described herein, and includes a controller including a microprocessor circuit and an interface circuit connected to the resolver, wherein the microprocessor circuit includes a dual-core central processing unit (CPU), a pulse generator, a sigma-delta analog-to-digital converter (SDADC), a global memory device, an internal communication bus and a direct memory access device (DMA). The microprocessor circuit is disposed to control the pulse generator to generate an excitation pulse transferable to the excitation winding of the resolver, and control the SDADC to capture data from the secondary windings of the resolver and store the captured data in the memory buffer. A control routine is executed to detect an envelope for the captured data, and a rotor position for the resolver is determined based upon the detected envelope.