A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol.

An apparatus includes a bi-phase mark coded (BMC) input port configured to receive BMC signals from a universal serial bus (USB) cable. The apparatus further includes a threshold adjustment circuit configured to generate a threshold, and a comparator configured to compare an input BMC signal from the BMC input port and the threshold and based on the comparison, generate an adjusted input BMC signal. The threshold adjustment circuit is further configured to adjust the threshold based upon the input BMC signal.

An electronic device is provided processor configured to: receive a biological signal of a user; detect whether the electronic device is attached to or detached from the user based on at least the biological signal; and control an I/O device operationally connected to the electronic device based on whether the electronic device is attached to or detached from the user.

An electronic device includes a communication unit that communicates with a battery, a storage unit that stores a first identification information of the battery, and a determination unit that determines whether the communication unit is capable of performing a predetermined communication with the battery, in a case where a second identification information of the battery received from the battery is matched with the first identification information stored in the storage unit.

In an embodiment, a host system for selecting a power supply includes a processor, a bus interface to connect to a peripheral device, and a power controller. The power controller may be to: determine whether the processor has entered a reduced power mode; determine, via one or more bus messages, whether charging is to be performed for a battery of the peripheral device; and in response to a determination that the processor has entered the reduced power mode and that charging is not to be performed for the battery of the peripheral device, switch from a first power supply to a second power supply as an active power source of the host system. Other embodiments are described and claimed.

Systems and techniques for automated transfer of peripheral device operations are described herein. In an example, a system may adapted so that, while a first device of a first type and a second device of the first type are simultaneously connected to a client device, the first device, rather than the second device, is used as an active device of the first type for at least one application, the first and second devices being peripheral devices. The system may be further adapted so that, while both the first and second devices remain connected to the client device, a switch from the first device to the second device by a user is determined, and, based on the switch from the first device to the second device, the second device, rather than the first device, is used as the active device of the first type for the at least one application.

Described are an information handling system, peripheral devices, and methods to connect the information handling or host to the peripheral devices. Physical connections connect the host with the one or more peripheral devices and the peripheral devices with one another. Electrical and communication connections connect the host with the one or more peripheral devices and the peripheral devices with one another. Power and power management are provided by the host through the electrical connection. An input from the host to the peripheral devices is used to establish communication flow between the host and the peripheral devices.

Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.

A processor can be configured to access boot firmware from a remote location independent from use of a chipset. After a processor powers-on or reboots, the processor can execute microcode. The microcode will cause the processor to train a link with a remote device. The remote device can provide the processor with access to boot firmware. The processor can copy the boot firmware to the processor's cache or memory. The processor will attempt to authenticate the boot firmware. If the boot firmware is authenticated, the processor executes the copy of the boot firmware.

Disclosed herein are methods, devices, and systems for providing timing and bandwidth management of ultra-wideband, wireless data channels (including radio frequency and wireless optical data channels). According to one embodiment, a hub adapter includes a first high-speed computer peripheral interface, first digital circuitry coupled with the high-speed computer peripheral interface; and a first free-space-optical (FSO) transmitter coupled with the digital circuitry, and a first FSO receiver coupled with the digital circuitry. The first FSO transmitter is configured to transmit a data channel and an out-of-band control signal comprising timing information and bandwidth management information to a computer peripheral adapter and the data channel is configured to operate at a bit rate greater than 1 gigabits per second (Gbps).