An artificial intelligence chip and a data operation method are provided. The artificial intelligence chip receives a command carrying first data and address information and includes a chip memory, a computing processor, a base address register, and an extended address processor. The base address register is configured to access an extended address space in the chip memory. The extended address processor receives the command. The extended address processor determines an operation mode of the first data according to the address information. When the address information points to a first section of the extended address space, the extended address processor performs a first operation on the first data. When the address information points to a section other than the first section of the extended address space, the extended address processor notifies the computing processor of the operation mode and the computing processor performs a second operation on the first data.

An artificial intelligence chip and a data operation method are provided. The artificial intelligence chip receives a command carrying first data and address information and includes a chip memory, a computing processor, a base address register, and an extended address processor. The base address register is configured to access an extended address space in the chip memory. The extended address processor receives the command. The extended address processor determines an operation mode of the first data according to the address information. When the address information points to a first section of the extended address space, the extended address processor performs a first operation on the first data. When the address information points to a section other than the first section of the extended address space, the extended address processor notifies the computing processor of the operation mode and the computing processor performs a second operation on the first data.

A server includes a normal NIC as an NIC having an expansion function, and a virtual patch panel having a transfer function of transferring packets between the normal NIC and an accelerator utilization type NIC, which is implemented by software. The server is configured such that, when a packet is transferred between the normal NIC and the accelerator utilization type NIC via the virtual patch panel, the target function transfers the packet to and from the APLs.

Methods and apparatus for an extended inter-kernel communication protocol for discovery of accelerator pools configured in a non-star mode. Under a discovery algorithm, discovery requests are sent from a root node to non-root nodes in the accelerator pool using an inter-kernel communication protocol comprising a data transmission protocol built over a Media Access Control (MAC) layer and transported over links coupled between IO ports on accelerators. The discovery requests are used to discover each of the nodes in the accelerator pool and determine the topology of the nodes. During this process, MAC address table entries are generated at the various nodes comprising (key, value) pairs of MAC IO port addresses identifying destination nodes and that may be reached by each node and the shortest path to reach such destination nodes. The discovery algorithm may also be used to discover storage related information for the accelerators. The accelerators may comprise FPGAs or other processing units, such as GPUs and Vector Processing Units (VPUs).

The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.

The present disclosure provides a method and a system for automatically configuring an I/O port. The method applied to a central processor includes: receiving request information from a controlled device, the request information carrying a type of a signal required by the controlled device, and sending, according to the type of the signal, a configuration instruction to a control device, and instructing the control device to configure the I/O port according to the configuration instruction. The controlled device is connected to the central processing unit, or the controlled device is connected to the central processor by means of the control device.

A universal peripheral extender architecture, system, and method is disclosed that addresses the need of communicatively connecting peripheral I/O devices and the smart host devices in legacy, medical, and industrial applications. As disclosed, a universal peripheral extender includes an I/O device translation & management module that has a device-side utility, a host-side I/O device translation & management utility, and a host/device translation & management scheduler utility.

A smart network interface card (SNIC) is provided. The SNIC may connect to an interconnect module (ICM) having at least two internal data paths. The SNIC and ICM determine a division of work between them. In general, NICs may be standard NICs, advanced NICs (ANICs), or smart NICs (SNICs). The ICM may perform a different amount of processing for network packets received from different devices based on the division of work previously identified. Some SNICs may preprocess network packets with respect to switching and routing processing to allow the ICM to bypass that functionality. Packets received from devices providing a division of work (e.g., SNICs) may receive reduced processing for functions offloaded to the SNIC. SNICs may utilize either a switching and routing group or a virtual bypass group such that data may bypass selected processing typically performed by the ICM.

A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.