A system, apparatus, and method for testing blocks of a system on a chip (SOC) are described herein. An SOC, in accordance with various embodiments, may include a serial communication interface configured to multiplex, serialize, and/or parallelize signals streams from selected blocks of the SOC to an off-chip test unit through an off-chip serial communication interface. Other embodiments may be described and claimed.

A computer, serving as a high-density server, includes a substrate, a plurality of connectors each including a plurality of electrodes, and a plurality of modules detachably attached to the substrate via connectors. The modules are attached to the connectors via different combinations of electrodes such that a first module (e.g. a CPU) is attached to one connector via a first combination of electrodes while a second module (e.g. a storage module or an attachment module) is attached to another connector via a second combination of electrodes. The connectors are aligned in a first direction on the substrate or in an array defined by first and second directions perpendicular to each other, wherein the connectors are selectively and electrically connected together with electrodes.

A method and apparatus for handling incoming data frames within a network interface controller. The network interface controller comprises at least one controller component operably coupled to at least one memory element. The at least one controller component is arranged to identify a next available buffer pointer from a pool of buffer pointers stored within a first area of memory within the at least one memory element, receive an indication that a start of a data frame has been received via a network interface, and allocate the identified next available buffer pointer to the data frame.

Certain embodiments herein relate to pairing an external device and a computer using a random user action. The random user action may be generated based on the type of device. After an external device is connected to the computer, the external device is segregated from one or more resources of the computer. A random user action based on the device type, and to be received from the external device, is generated and requested. If the random user action is received, the external device is paired with the computer and provided access to the one or more resources of the computer.

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

An expander I/O module discovery/management system includes a secondary system chassis housing an expander I/O module coupled to a server device. The server device identifies the secondary system chassis and an expander I/O module port utilized by that server device, and then generates and transmits an expander I/O module reporting communication identifying the secondary system chassis and the expander I/O module port. A primary system chassis houses a switching I/O module coupled to the expander I/O module. The switching I/O module receives the expander I/O module reporting communication and determines that the secondary system chassis identified in the expander I/O module reporting communication is different than the primary system chassis. In response, the switching I/O module assigns a virtual slot to the expander I/O module, and assigns a virtual port associated with the virtual slot to the expander I/O module port identified in the expander I/O module reporting communication.

Methods, systems, and devices for signal path biasing in an electronic system (e.g., a memory system) are described. In one example, a memory device, a host device, or both may be configured to bias a signal path, between an idle state and an information transfer or between an information transfer and an idle state, to an intermediate or mid-bias voltage level, which may reduce signal interference associated with such transitions. In various examples, the described biasing to a voltage, such as a mid-bias voltage, may be associated with an access command or other command for information to be communicated between devices of the electronic system, such as a command for information to be communicated between a memory device and a host device.

Methods, systems, and devices for signal path biasing in an electronic system (e.g., a memory system) are described. In one example, a memory device, a host device, or both may be configured to bias a signal path, between an idle state and an information transfer or between an information transfer and an idle state, to an intermediate or mid-bias voltage level, which may reduce signal interference associated with such transitions. In various examples, the described biasing to a voltage, such as a mid-bias voltage, may be associated with an access command or other command for information to be communicated between devices of the electronic system, such as a command for information to be communicated between a memory device and a host device.

An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller.

A platform development system and method in which configuration information for an information handling resource type, e.g., a network interface card, is obtained by accessing a first instance of the resource type. The configuration information includes one or more fixed elements and a corresponding number of variable elements. Configuration information may include attribute-value pairs in which the attribute field of each pair is the fixed part of the configuration information and the corresponding value field is the variable part. A simulation policy, indicative of the fixed part of the configuration information, may then be defined for the resource type of interest. The simulation policy, in conjunction with user-specified values for the variable part of the configuration information, may define configuration information for a second instance of the resource type. A management server simulator may then simulate the second instance of the resource type based on the applicable configuration information.