A write-enable circuit outputting a write-enable signal for digital data, in an analog-to-digital converter comprising a bus-controller connected to an external unit, an arithmetic processing unit performing data processing, and an arithmetic unit holding the data and having a normal access mode in which the data are temporarily written into the arithmetic processing unit and then written into the bus-controller and a high-speed access mode in which the data are written directly into the bus-controller. The circuit comprises an address-coincidence-determining circuit provided in the arithmetic unit outputting a write-enable signal from the arithmetic unit when a predetermined address for a memory of the bus-controller coincides with an address specified by the arithmetic processing unit; and a logic circuit inputting the write-enable signal to the bus-controller when the arithmetic processing unit asserts a high-speed access signal indicating that now is in the high-speed access mode.

A computing device including: more than two Universal Serial Bus (USB) ports configured to be connected respectively to more than two mobile devices simultaneously; at least one processor coupled to the USB ports; and a memory storing instructions configured to instruct the at least one processor to reprogram, through the more than two USB ports, the more than two mobile devices simultaneously.

A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first memory interface, a second memory controller configured to output a second control signal to the second external memory through a second memory interface, an inter-device interface for communicating with another semiconductor device, terminals configured to output the second control signal that has passed through the second memory interface, and a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode of the semiconductor device and to couple the selected interface to the terminals.

According to an example, a multi-mode agent may include a processor interconnect (PI) interface to receive data from a processor and to selectively route the data to a node controller logic block, a central switch, or an optical interface based on one of a plurality of modes of operation of the multi-mode agent. The modes of operation may include a glueless mode where the PI interface is to route the data directly to the optical interface and bypass the node controller logic block and the central switch, a switched glueless mode where the PI interface is to route the data directly to the central switch for routing to the optical interface, and bypass the node controller logic block, and a glued mode where the PI interface is to route the data directly to the node controller logic block for routing to the central switch and further to the optical interface.

A remote access appliance is disclosed which provides electronic display identification data (EDID) information associated with a monitor which is communicating with the appliance, to any one of a plurality of remote computers in communication with the appliance, without requiring rebooting of a selected one of the remote computers. A plurality of multiplexers is controlled by a controller for interfacing a selected one of the computers to a display data channel (DDC) interface associated with the monitor. Memory devices are accessible by each of the computers and by the controller which store the EDID information. The controller controls the multiplexers so that any selected one of the computers can communicate with the monitor, and can access an associated one of the memory devices to obtain the stored EDID information, or such that the EDID information can be loaded into each of the memory devices.

An interconnect module (ICM) having at least two internal data paths is provided. The ICM determines if a connected network interface card (NIC) supports a division of work between the NIC and the ICM. NICs may be standard NICs, advanced NICs (ANICs), or smart NICs (SNICs). The ICM may perform a different amount of processing for network packets received from different devices based on the division of work previously identified. Some NICs may preprocess network packets with respect to switching and routing processing to allow the ICM to bypass that functionality for those packets. Packets received from devices not providing a division of work receive full processing including switching and routing processing. Devices may be grouped to either a switching and routing group or a virtual bypass group such that data received from devices associated with the virtual bypass group may bypass selected processing typically performed by the ICM.

Enhanced apparatuses, systems, and techniques for coupling network-linked peripheral devices into host computing devices is presented. A method includes, over a network interface of a host device, obtaining an indication of a peripheral device available for associating with the host device. Based on the indication, the method includes initiating instantiation of the peripheral device into a Peripheral Component Interconnect Express (PCIe) subsystem of the host device by at least emulating behavior of the peripheral device over the network interface as a PCIe peripheral device coupled locally to the host system.

A system and method communicates with one of two or more secure digital input output (SDIO) units that only one SDIO unit responds when it is being addressed. The SDIO unit has an SDIO clock input port, an SDIO data bus output port, and an SDIO bidirectional command port. Each SDIO unit has an address indicator within it associated with each SDIO unit. An SDIO unit will not respond to an SDIO command unless an SDIO unit address encoded in the SDIO command matches its address indicator.

A method is disclosed for requesting data in a cloud gaming system that includes a cloud storage system and a cloud compute system, each of which has a respective peripheral component interconnect express (PCIe) interface and a respective computer memory. The cloud gaming system includes a PCIe switch connected to both the PCIe interface of the cloud storage system and the PCIe interface of the cloud compute system. The PCIe switch exposes a doorbell register that is monitored by the cloud storage system. The cloud compute system writes to the doorbell register, which causes an interrupt to fire on the cloud storage system. The cloud storage system handles the interrupt, which directs the cloud storage system to read a message from a specified computer memory location. The message directs the cloud storage system to read requested data from a storage device accessible by the cloud storage system.

Implementations of the present disclosure provide computer-implemented methods including defining a workload comprising a plurality of service requests, each service request corresponding to a class of a plurality of classes, applying the workload to a computer system that receives and processes service requests, measuring a response time of the computer system for each request of the workload, estimating a mean service demand for each class based on the response times and a base queuing model that represents the computer system, and generating the queuing model based on the mean service demands and characteristics of the workload.