An apparatus includes an interface with a plurality of channels; a multiplexer coupled to the interface and configured to couple transmit circuitry to a first channel mapped as a transmit path in a channel configuration and to couple receive circuitry to a second channel mapped as a receive path in the channel configuration; and a controller coupled to the multiplexer. The controller may be configured to perform the steps including determining a figure of merit of at least one channel of the plurality of channels of the interface; determining the channel configuration mapping transmit and receive paths to the plurality of the channels of the interface; and controlling the multiplexer to couple transmit circuitry to the first channel mapped as a transmit path in the channel configuration and to couple receive circuitry to the second channel mapped as a receive path in the channel configuration for dynamic channel swap(s).

Described embodiments provide systems and methods for providing data loss prevention via an embedded browser. An interprocess communication (IPC) manager may interface with an embedded browser to control the transfer of data from a first application to a second application in accordance with a policy. The IPC manager may detect a command to store data accessed on the first application via the embedded browser and store the data onto a secure container. The secure container may be dedicated to the embedded browser. The IPC manager may subsequently detect a command to retrieve data from the secure container and to replicate the data onto the second application. The IPC manager may determine a policy to apply to the data. The policy may specify whether the data from the first application is permitted to be replicated onto the second application. The IPC manager may subsequently replicate the data on the second application.

Described embodiments provide systems and methods for providing data loss prevention via an embedded browser. An interprocess communication (IPC) manager may interface with an embedded browser to control the transfer of data from a first application to a second application in accordance with a policy. The IPC manager may detect a command to store data accessed on the first application via the embedded browser and store the data onto a secure container. The secure container may be dedicated to the embedded browser. The IPC manager may subsequently detect a command to retrieve data from the secure container and to replicate the data onto the second application. The IPC manager may determine a policy to apply to the data. The policy may specify whether the data from the first application is permitted to be replicated onto the second application. The IPC manager may subsequently replicate the data on the second application.

A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.

A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.

A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

A reconfigurable hardware platform uses, in place of a portion of software, a chain of reconfigurable hardware Operator Blocks to manipulate data as the data moves down the chain. This conveyor belt architecture, or chain of Operator Blocks, moves data from Operator Block to Operator Block. This conveyor belt architecture processor may be combined with a conventional front-end processor to process complex information or critical loops in hardware while processing a rest of a program as software.

A reconfigurable hardware platform uses, in place of a portion of software, a chain of reconfigurable hardware Operator Blocks to manipulate data as the data moves down the chain. This conveyor belt architecture, or chain of Operator Blocks, moves data from Operator Block to Operator Block. This conveyor belt architecture processor may be combined with a conventional front-end processor to process complex information or critical loops in hardware while processing a rest of a program as software.

The invention relates to a system for establishing a data connection between a master unit (M) and at least one device unit (D), wherein the master unit (M) is coupled to a primary coupler unit (D.sub.prim) and the at least one device unit (D) is coupled to a secondary coupler unit (D.sub.sec), in each case for electrical power transmission and for data transmission. The primary coupler unit (D.sub.prim) and the secondary coupler unit (D.sub.sec) can be coupled for data transmission. A control signal can be received and the system has three operating states that can be activated in dependence on the received control signal. When the first operating state is activated, there is a data connection according to the IO-Link standard between the master unit (M) and the device unit (D). When the second operating state is activated, primary coupler identification data (D.sub.prim-ID) are allocated to the primary coupler unit (D.sub.prim), wherein there is a data connection according to the IO-Link standard between the master unit (M) and the primary coupler unit (D.sub.prim). When the third operating state is activated, secondary coupler Identification date (D.sub.secID) are allocated to the secondary coupler unit (D.sub.sec), wherein there is a data connection according to the IO-Link standard between the master unit (M) and the secondary coupler unit (D.sub.sec). The invention furthermore relates to a method for operating the system.