Technologies for providing I/O channel abstraction for accelerator device kernels include an accelerator device comprising circuitry to obtain availability data indicative of an availability of one or more accelerator device kernels in a system, including one or more physical communication paths to each accelerator device kernel. The circuitry is also configured to determine whether to establish a logical communication path between a kernel of the present accelerator device and another accelerator device kernel and establish, in response to a determination to establish the logical communication path as a function of the obtained availability data, the logical communication path between the kernel of the present accelerator device and the other accelerator device kernel.

Technologies for providing I/O channel abstraction for accelerator device kernels include an accelerator device comprising circuitry to obtain availability data indicative of an availability of one or more accelerator device kernels in a system, including one or more physical communication paths to each accelerator device kernel. The circuitry is also configured to determine whether to establish a logical communication path between a kernel of the present accelerator device and another accelerator device kernel and establish, in response to a determination to establish the logical communication path as a function of the obtained availability data, the logical communication path between the kernel of the present accelerator device and the other accelerator device kernel.

A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

An integrated circuit device has a processor, a software-trace message handling system, a software-trace message sink peripheral, and a hardware interconnect system. The interconnect system is capable of directing software-trace messages from the processor to the software-trace message handling system, and of directing software-trace messages from the processor to the software-trace message sink peripheral. The software-trace message sink peripheral can present an interconnect delay to the processor, when receiving a software-trace message from the processor, that is equal to or substantially equal to an interconnect delay that the software-trace message handling system would have presented to the processor if the software-trace message handling system were to have received the software-trace message.

An integrated circuit device has a processor, a software-trace message handling system, a software-trace message sink peripheral, and a hardware interconnect system. The interconnect system is capable of directing software-trace messages from the processor to the software-trace message handling system, and of directing software-trace messages from the processor to the software-trace message sink peripheral. The software-trace message sink peripheral can present an interconnect delay to the processor, when receiving a software-trace message from the processor, that is equal to or substantially equal to an interconnect delay that the software-trace message handling system would have presented to the processor if the software-trace message handling system were to have received the software-trace message.

Embodiments using a distributed bus arbiter for one cycle channel selection with inter-channel ordering constraints. A distributed bus arbiter that orders one or more memory bus transactions originating from a plurality of master bus components to a plurality of shared remote slaves over shared serial channels attached to differing interconnect instances may be implemented.

In one embodiment, a method for method for managing a virtual service in an information handling system includes: identifying, by a virtual image of a plurality of virtual images of the virtual service, a device setting to be modified, the device setting associated with a device of the information handling system, each of the plurality of virtual images having respective device settings; accessing, by a host service, a protected namespace of a plurality of protected namespaces, the protected namespace associated with the virtual image; identifying, by the host service, a device index stored in the protected namespace, the device index pointing to a device-specific function associated with the device, the device-specific function stored in a translation table; accessing, by the host service, the device-specific function stored in the translation table based on the device index; and causing, by the host service, the device-specific function to modify the device setting.

In one embodiment, a method for method for managing a virtual service in an information handling system includes: identifying, by a virtual image of a plurality of virtual images of the virtual service, a device setting to be modified, the device setting associated with a device of the information handling system, each of the plurality of virtual images having respective device settings; accessing, by a host service, a protected namespace of a plurality of protected namespaces, the protected namespace associated with the virtual image; identifying, by the host service, a device index stored in the protected namespace, the device index pointing to a device-specific function associated with the device, the device-specific function stored in a translation table; accessing, by the host service, the device-specific function stored in the translation table based on the device index; and causing, by the host service, the device-specific function to modify the device setting.

A smart network interface card (SNIC) is provided. The SNIC may connect to an interconnect module (ICM) having at least two internal data paths. The SNIC and ICM determine a division of work between them. In general, NICs may be standard NICs, advanced NICs (ANICs), or smart NICs (SNICs). The ICM may perform a different amount of processing for network packets received from different devices based on the division of work previously identified. Some SNICs may preprocess network packets with respect to switching and routing processing to allow the ICM to bypass that functionality. Packets received from devices providing a division of work (e.g., SNICs) may receive reduced processing for functions offloaded to the SNIC. SNICs may utilize either a switching and routing group or a virtual bypass group such that data may bypass selected processing typically performed by the ICM.