Dynamic lane management for interference mitigation is disclosed. In one aspect, an integrated circuit (IC) is provided that employs a control system configured to mitigate electromagnetic interference (EMI) caused by an aggressor communications bus. The control system is configured to receive information related to EMI conditions and adjust which lanes of the aggressor communications bus are employed for signal transmission. The IC includes an interface configured to couple to the aggressor communications bus. The interface is configured to transmit signals to and receive signals from the aggressor communications bus. The control system is configured to use the information related to the EMI conditions to assign signals to be transmitted via particular lanes of the aggressor communications bus to mitigate the EMI experienced by a victim receiver. The control system provides designers with an additional tool that may reduce the performance degradation of the victim receiver attributable to EMI.

The present disclosure relates to a method for inter-core communication of a multi-core processor, a processor, an inter-core communication system and a computer readable storage medium. The method for inter-core communication comprises: receiving a communication request sent by an initiating core for communication with receiving cores; and instructing, on the basis of the communication request, the initiating core to communicate with the receiving cores by using a delivery message to invoke interfaces of services in the receiving cores; wherein the delivery message is service-oriented and corresponds to the interfaces of the services in the receiving cores. According to the method for inter-core communication of the present disclosure, services built in various systems can interact in a uniform and universal manner by means of the service-oriented delivery message. Therefore, the portability of application programs located on different cores can be improved, and the development difficulty is reduced.

Techniques are disclosed for peer-to-peer data transfers where a source device receives a request to read data words from a target device. The source device creates a first and second read command for reading a first portion and a second portion of a plurality of data words from the target device, respectively. The source device transmits the first read command to the target device, and, before a first read operation associated with the first read command is complete, transmits the second read command to the target device. The first and second portions of the plurality of data words are stored in a first and second portion a buffer memory, respectively. Advantageously, an arbitrary number of multiple read operations may be in progress at a given time without using multiple peer-to-peer memory buffers. Performance for large data block transfers is improved without consuming peer-to-peer memory buffers needed by other peer GPUs.

Techniques are disclosed for peer-to-peer data transfers where a source device receives a request to read data words from a target device. The source device creates a first and second read command for reading a first portion and a second portion of a plurality of data words from the target device, respectively. The source device transmits the first read command to the target device, and, before a first read operation associated with the first read command is complete, transmits the second read command to the target device. The first and second portions of the plurality of data words are stored in a first and second portion a buffer memory, respectively. Advantageously, an arbitrary number of multiple read operations may be in progress at a given time without using multiple peer-to-peer memory buffers. Performance for large data block transfers is improved without consuming peer-to-peer memory buffers needed by other peer GPUs.

Provided are a method and device for audio post-processing. The method may comprise receiving, at a first processor, an audio signal, detecting, at the first processor, a plurality of post-processing modules for altering the audio signal, and creating, based on information identifying functions of the plurality of post-processing modules, an optimized acceleration module. It may further comprise sending, through the optimized acceleration module, a buffer packet of the audio signal along a single data path to a second processor and post-processing, at the second processor, the buffer packet of the audio signal through each of a plurality of associated post-processing modules that correspond to the post-processing modules on the first processor, controlling each associated post-processing module via control paths from each corresponding post-processing module, and receiving, at the first processor, a post-processed buffer packet of the audio signal via a single return data path.

Provided are a method and device for audio post-processing. The method may comprise receiving, at a first processor, an audio signal, detecting, at the first processor, a plurality of post-processing modules for altering the audio signal, and creating, based on information identifying functions of the plurality of post-processing modules, an optimized acceleration module. It may further comprise sending, through the optimized acceleration module, a buffer packet of the audio signal along a single data path to a second processor and post-processing, at the second processor, the buffer packet of the audio signal through each of a plurality of associated post-processing modules that correspond to the post-processing modules on the first processor, controlling each associated post-processing module via control paths from each corresponding post-processing module, and receiving, at the first processor, a post-processed buffer packet of the audio signal via a single return data path.

Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.

A multi-chip system and a data transmission method thereof are provided. The multi-chip system includes a first chip, a link unit, and a second chip. The first chip includes multiple transmitter (TX) channels and a first data processing module. The TX channels are configured to provide at least one transaction information. The first data processing module converts the at least one transaction information into at least one first data packet according to a general packet format and packs the at least one first data packet according to a specific packet format to generate a second data packet. The first data processing module merges two sets of second data packets into a third data packet and transmits the third data packet to the link unit. The second chip receives the third data packet through the link unit.

Methods and apparatus for enhancing simulated annealing with quantum fluctuations. In one aspect, a method includes obtaining an input state; performing simulated annealing on the input state with a temperature reduction schedule until a decrease in energy is below a first minimum value; terminating the simulated annealing in response to determining that the decrease in energy is below the first minimum level; outputting a first evolved state and first temperature value; reducing the temperature to a minimum temperature value; performing quantum annealing on the first evolved state with a transversal field increase schedule until a completion of a second event occurs; terminating the quantum annealing in response to determining that a completion of the second event has occurred; outputting a second evolved state as a subsequent input state for the simulated annealing, and determining that the completion of the first event has occurred.

Methods and apparatus for enhancing simulated annealing with quantum fluctuations. In one aspect, a method includes obtaining an input state; performing simulated annealing on the input state with a temperature reduction schedule until a decrease in energy is below a first minimum value; terminating the simulated annealing in response to determining that the decrease in energy is below the first minimum level; outputting a first evolved state and first temperature value; reducing the temperature to a minimum temperature value; performing quantum annealing on the first evolved state with a transversal field increase schedule until a completion of a second event occurs; terminating the quantum annealing in response to determining that a completion of the second event has occurred; outputting a second evolved state as a subsequent input state for the simulated annealing, and determining that the completion of the first event has occurred.