G06F15/82

Automatic qubit calibration
11567842 · 2023-01-31 · ·

Methods and apparatus for automatic qubit calibration. In one aspect, a method includes obtaining a plurality of qubit parameters and data describing dependencies of the plurality of qubit parameters on one or more other qubit parameters; identifying a qubit parameter; selecting a set of qubit parameters that includes the identified qubit parameter and one or more dependent qubit parameters; processing one or more parameters in the set of qubit parameters in sequence according to the data describing dependencies, comprising, for a parameter in the set of qubit parameters: performing a calibration test on the parameter; and performing a first calibration experiment or a diagnostic calibration algorithm on the parameter when the calibration test fails.

Automatic qubit calibration
11567842 · 2023-01-31 · ·

Methods and apparatus for automatic qubit calibration. In one aspect, a method includes obtaining a plurality of qubit parameters and data describing dependencies of the plurality of qubit parameters on one or more other qubit parameters; identifying a qubit parameter; selecting a set of qubit parameters that includes the identified qubit parameter and one or more dependent qubit parameters; processing one or more parameters in the set of qubit parameters in sequence according to the data describing dependencies, comprising, for a parameter in the set of qubit parameters: performing a calibration test on the parameter; and performing a first calibration experiment or a diagnostic calibration algorithm on the parameter when the calibration test fails.

Anti-congestion flow control for reconfigurable processors

A compiler configured to configure memory nodes with a ready-to-read credit counter and a write credit counter. The ready-to-read credit counter of a particular upstream memory node initialized with as many read credits as a buffer depth of a corresponding downstream memory node. The ready-to-read credit counter configured to decrement when a buffer data unit is written by the particular upstream memory node into the corresponding downstream memory node, and to increment when the particular upstream memory node receives from the corresponding downstream memory node a read ready token. The write credit counter of the particular upstream memory node initialized with one or more write credits and configured to decrement when the particular upstream memory node begins writing the buffer data unit into the corresponding downstream memory node, and to increment when the particular upstream memory node receives from the corresponding downstream memory node a write done token.

DETERMINING INTERNODAL PROCESSOR INTERCONNECTIONS IN A DATA-PARALLEL COMPUTING SYSTEM
20230229624 · 2023-07-20 · ·

A computer-implemented method comprises a topological communications configurator (TCC) of a computing system determining a connections-optimized configuration of processors among compute nodes of the system. Processors included in the compute nodes can execute compute workers of an application of the system and can form intranodal segments of an internodal interconnection topology communicatively coupling the intranodal segments. The intranodal segments can be interconnected via an internodal interconnections fabric. The TCC can determine the connections-optimized configuration based on internodal communications costs corresponding to communications routes among the internodal segments via the internodal interconnection fabric. The computing system can comprise the TCC and can comprise a data-parallel computing system.

Variation-aware qubit movement scheme for noise intermediate scale quantum era computers

Systems and methods for efficiently routing qubits in a quantum computing system include selecting bubble nodes and routing qubits to the bubble nodes. The systems and methods further include dividing a system of nodes into regions and selecting a bubble node for each region. The systems and methods further include using super bubble nodes with reliable links connected to other super bubble nodes and bubble nodes to improve cross-region operations.

Variation-aware qubit movement scheme for noise intermediate scale quantum era computers

Systems and methods for efficiently routing qubits in a quantum computing system include selecting bubble nodes and routing qubits to the bubble nodes. The systems and methods further include dividing a system of nodes into regions and selecting a bubble node for each region. The systems and methods further include using super bubble nodes with reliable links connected to other super bubble nodes and bubble nodes to improve cross-region operations.

Calibration of quantum processor operator parameters
11699088 · 2023-07-11 · ·

Methods, systems and apparatus for determining operating parameters for a quantum processor including multiple interacting qubits. In one aspect, a method includes generating a graph of nodes and edges, wherein each node represents a respective qubit and is associated with an operating parameter of the respective qubit, and wherein each edge represents a respective interaction between two qubits and is associated with an operating parameter of the respective interaction; selecting an algorithm that traverses the graph based on a traversal rule; identifying one or multiple disjoint subsets of nodes or one or multiple disjoint subsets of edges, wherein nodes in a subset of nodes and edges in a subset of edges are related via the traversal rule; and determining calibrated values for the nodes or edges in each subset using a stepwise constrained optimization process where constraints are determined using previously calibrated operating parameters.

Calibration of quantum processor operator parameters
11699088 · 2023-07-11 · ·

Methods, systems and apparatus for determining operating parameters for a quantum processor including multiple interacting qubits. In one aspect, a method includes generating a graph of nodes and edges, wherein each node represents a respective qubit and is associated with an operating parameter of the respective qubit, and wherein each edge represents a respective interaction between two qubits and is associated with an operating parameter of the respective interaction; selecting an algorithm that traverses the graph based on a traversal rule; identifying one or multiple disjoint subsets of nodes or one or multiple disjoint subsets of edges, wherein nodes in a subset of nodes and edges in a subset of edges are related via the traversal rule; and determining calibrated values for the nodes or edges in each subset using a stepwise constrained optimization process where constraints are determined using previously calibrated operating parameters.

Method and system for a semi-dictatorial determination of stackable system roles in an information handling system

A method for managing information handling system includes obtaining, by a zone-leading information handling system of the set of information handling systems, a first hardware resource information entry from a first information handling system in a first zone, obtaining a second hardware resource information entry from a second information handling system in the first zone, performing a stackable system role (SSR) entry analysis based on the first hardware resource information entry and the second hardware resource information entry, determining a set of SSRs, wherein each SSR in the set of SSRs corresponds to each of: the first information handling system, the second information handling system, and the zone-leading information handling system, initiating a SSR distribution of SSR entries based on the set of SSRs.

Method and system for a semi-dictatorial determination of stackable system roles in an information handling system

A method for managing information handling system includes obtaining, by a zone-leading information handling system of the set of information handling systems, a first hardware resource information entry from a first information handling system in a first zone, obtaining a second hardware resource information entry from a second information handling system in the first zone, performing a stackable system role (SSR) entry analysis based on the first hardware resource information entry and the second hardware resource information entry, determining a set of SSRs, wherein each SSR in the set of SSRs corresponds to each of: the first information handling system, the second information handling system, and the zone-leading information handling system, initiating a SSR distribution of SSR entries based on the set of SSRs.