A power intent may be loaded on an integrated circuit (IC) design, where the power intent may be represented by a set of constraints. A logic network may be constructed based on the set of constraints and a rule check which is desired to be performed on the power intent. In response to a failure of the rule check, one or more refutation proofs may be created based on the logic network. A subset of the set of constraints may be identified based on the one or more refutation proofs, where the subset of the set of constraints may include an inconsistency which caused the rule check to fail.

A power intent may be loaded on an integrated circuit (IC) design, where the power intent may be represented by a set of constraints. A logic network may be constructed based on the set of constraints and a rule check which is desired to be performed on the power intent. In response to a failure of the rule check, one or more refutation proofs may be created based on the logic network. A subset of the set of constraints may be identified based on the one or more refutation proofs, where the subset of the set of constraints may include an inconsistency which caused the rule check to fail.

Embodiments of the present disclosure provide methods, apparatus, systems, computer program products for transferring a performance of a procedure found in technical documentation for an item via an interactive electronic technical manual system (IETM) configured to provide electronic and credentialed access to the technical documentation. In one embodiment, a method is provided comprising: providing the steps of the procedure in an order in which the steps are to be carried out; and while a user is participating in the performance of the procedure: causing a particular step that is being carried out to be highlighted; receiving input of a selection of a transfer mechanism and in response: causing an indication to be displayed between the particular step and a next step to be carried out identifying where the performance has been suspended; providing a transfer window displaying transfer information; and recording the transfer information and an identifier for the indication.

A system and a method are disclosed for placing hardware components on a printed circuit board (“PCB”) in a way that enables all hardware components on the PCB to be passively cooled without using active cooling systems. Components are selected to be placed onto the PCB and heat metrics for each component is obtained (e.g., from a server). The components are ranked based on the amount of heat that each component generates. A corresponding position for each of the hardware components is determined based on the ranking of the components and the orientation of the PCB. The placement is based on the concept that air having higher temperature rises while air having cooler temperature falls. A representation of the PCB according to corresponding positions of the hardware components may be generated for display.

A system and a method are disclosed for placing hardware components on a printed circuit board (“PCB”) in a way that enables all hardware components on the PCB to be passively cooled without using active cooling systems. Components are selected to be placed onto the PCB and heat metrics for each component is obtained (e.g., from a server). The components are ranked based on the amount of heat that each component generates. A corresponding position for each of the hardware components is determined based on the ranking of the components and the orientation of the PCB. The placement is based on the concept that air having higher temperature rises while air having cooler temperature falls. A representation of the PCB according to corresponding positions of the hardware components may be generated for display.

A computing system may include a hyperspace generation engine and a hyperspace processing engine. The hyperspace generation engine may be configured to access a feature vector set, and feature vectors in the feature vector set may represent values for multiple parameters of data points in a dataset. The hyperspace generation engine may further be configured to perform a principal component analysis on the feature vector set and quantize the principal component space into a hyperspace comprised of hyperboxes. The hyperspace processing engine may be configured to process the dataset according to a mapping of the feature vector set into the hyperboxes of the hyperspace.

A computing system may include a hyperspace generation engine and a hyperspace processing engine. The hyperspace generation engine may be configured to access a feature vector set, and feature vectors in the feature vector set may represent values for multiple parameters of data points in a dataset. The hyperspace generation engine may further be configured to perform a principal component analysis on the feature vector set and quantize the principal component space into a hyperspace comprised of hyperboxes. The hyperspace processing engine may be configured to process the dataset according to a mapping of the feature vector set into the hyperboxes of the hyperspace.

A computer-implemented method of designing at least a portion of an electronic circuit schematic is described herein. The method comprises receiving requirements for an electronic circuit or at least a portion of an electronic circuit, creating a set of variables and constraints based on the requirements for the electronic circuit, wherein the constraints limit the possible value that may be assigned to the variables, assigning values to the variables using a solver such that the values of the variables satisfy the constraints, and outputting at least a portion of a designed electronic circuit schematic or circuit schematic specification that meets the requirements for the electronic circuit based on the assigned values of the variables.

A computer-implemented method of designing at least a portion of an electronic circuit schematic is described herein. The method comprises receiving requirements for an electronic circuit or at least a portion of an electronic circuit, creating a set of variables and constraints based on the requirements for the electronic circuit, wherein the constraints limit the possible value that may be assigned to the variables, assigning values to the variables using a solver such that the values of the variables satisfy the constraints, and outputting at least a portion of a designed electronic circuit schematic or circuit schematic specification that meets the requirements for the electronic circuit based on the assigned values of the variables.

Embodiments are for using design context projection and wire editing in augmented media. Responsive to receiving an indication of an error in a design for an integrated circuit (IC), a localized area is extracted encompassing the error in the design. Augmented reality media of the localized area of the design is generated with a guide pattern, the localized area including objects. The augmented reality media of the localized area is caused to be presented in a three-dimensional (3D) projection on an augmented reality device for a user. Responsive to receiving at least one modification to the augmented media in the 3D projection, the design for the IC is updated with the modifications.