A graphical programming method, system and apparatus, a medium, a processor and a terminal are disclosed. The method includes displaying a first component including at least one port, in an interface; displaying a second component including at least one port, in an interface; in response to an operation of a user, enabling the second component to move, in the interface, towards the first component; and in response to a distance between a port of the second component and a port of the first component being less than a threshold distance, automatically forming a connecting line between the first component and the second component, two ends of the connecting line being respectively connected to a port of the first component and a port of the second component. As such, time consumption of interaction in graphical programming is reduced, programming time of a user is saved, and graphical programming efficiency is improved.

This disclosure relates to signal observability rating. In an example, a method can include propagating a clock signal through a respective module of a circuit design in a forward and backward direction, evaluating clock signal propagation results for the respective module based on a forward and backward clock signal propagation of the clock signal to compute an observability rating for a data signal to be processed by the respective module during formal verification, and updating a current observability rating of the respective property for the data signal to the computed observability rating.

This disclosure relates to signal observability rating. In an example, a method can include propagating a clock signal through a respective module of a circuit design in a forward and backward direction, evaluating clock signal propagation results for the respective module based on a forward and backward clock signal propagation of the clock signal to compute an observability rating for a data signal to be processed by the respective module during formal verification, and updating a current observability rating of the respective property for the data signal to the computed observability rating.

Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect(LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design. According to some embodiments, conducting placement and optimization further includes: moving the at least one spare cells to locations to abut the at least one timing critical cells to form pattern-S for each of the at least one timing critical cells.

The present invention belongs to the technical field of simulation of power semiconductor modules, and discloses a multi-physics co-simulation method of a power semiconductor module. The multi-physics co-simulation method of the power semiconductor module comprises: adopting professional circuit simulation software PSpice supporting a spice model to be imported into a device, and by designing a specific collaborative analysis method and performing secondary development of a software data exchange interface, i.e. constructing a coupling interface of co-simulation, performing electricity-heat-force co-simulation of two types of software PSpice and COMSOL by adopting an indirect coupling manner. The simulation time is greatly shortened, and the simulation efficiency is improved.

The present invention belongs to the technical field of simulation of power semiconductor modules, and discloses a multi-physics co-simulation method of a power semiconductor module. The multi-physics co-simulation method of the power semiconductor module comprises: adopting professional circuit simulation software PSpice supporting a spice model to be imported into a device, and by designing a specific collaborative analysis method and performing secondary development of a software data exchange interface, i.e. constructing a coupling interface of co-simulation, performing electricity-heat-force co-simulation of two types of software PSpice and COMSOL by adopting an indirect coupling manner. The simulation time is greatly shortened, and the simulation efficiency is improved.

Approaches for visualizing data buses in a circuit design include determining ones of the data buses that satisfy selection criteria. For each element connected to a data bus of the ones of the data buses, a method and system determine whether the element is of interest or the element is not of interest. A graphical representation of the ones of the data buses and each element of interest is generated, and data buses of the circuit design determined to not satisfy the selection criteria and elements not of interest are excluded from the graphical representation. The graphical representation is displayed on a display device.

Approaches for visualizing data buses in a circuit design include determining ones of the data buses that satisfy selection criteria. For each element connected to a data bus of the ones of the data buses, a method and system determine whether the element is of interest or the element is not of interest. A graphical representation of the ones of the data buses and each element of interest is generated, and data buses of the circuit design determined to not satisfy the selection criteria and elements not of interest are excluded from the graphical representation. The graphical representation is displayed on a display device.

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a netlist associated with an electronic design and performing genetic optimization on a portion of the netlist to identify and place one or more capacitors on a printed circuit board to minimize an impedance associated with a power plane. Embodiments may further include displaying, at a graphical user interface, a placement of the one or more capacitors, wherein the placement is based upon, at least in part, the performing.

Disclosed embodiments herein relate to an integrated circuit including power switches with active regions connected to form a contiguous region. In one aspect, the integrated circuit includes a first layer including a first metal rail extending in a first direction. In one aspect, the integrated circuit includes a second layer above the first layer along a second direction perpendicular to the first direction. The second layer may include active regions for power switches. In one aspect, the active regions of the power switches are connected to form a contiguous region extending in the first direction. The first metal rail may be electrically coupled to the active regions through via contacts. In one aspect, the integrated circuit includes a third layer above the second layer along the second direction. The third layer may include a second metal rail electrically coupled to some of the power switches through additional via contacts.