A method and a system for recording an integrated circuit version are provided. The method is adapted to a register in an integrated circuit, which includes the following steps: recording the integrated circuit version with N bits, in which N is an integer greater than 1; and amending only a bit value of at least one bit selected from the N bits that have not been used for denoting any past integrated circuit version each time when the integrated circuit is revised.

System and methods are disclosed for transformation of a network, such as a network-on-chip (NoC). The system applies a method of clustering to nodes and edges. The clustering transforms the network and produces a deadlock free and (near-)optimal network that honors the constraints of the input network's floorplan and specification.

System and methods are disclosed for transformation of a network, such as a network-on-chip (NoC). The system applies a method of clustering to nodes and edges. The clustering transforms the network and produces a deadlock free and (near-)optimal network that honors the constraints of the input network's floorplan and specification.

A tool makes modifications to the chip floorplan and the network-on-chip (NoC) elements’ position on the floorplan and updates the number and position of the pipeline elements in a pipeline stage automatically, resulting in fewer errors and higher productivity.

Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.

Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.

A method of generating training data for training a Machine Learning based Task Contention Model, ML based TCM, to predict time delays resulting from contention between tasks running in parallel on a multi-processor system is provided herein. The method includes: executing a plurality of microbenchmarks, μBenchmarks B.sub.j, on the multi-processor system in isolation and measuring a number of resultant Performance Monitoring Counters, PMCs, over time to extract ideal characteristic footprints of each μBenchmark when operating in isolation; performing a feature correlation analysis on the PMCs resulting from the plurality of μBenchmarks to determine the degree of correlation between each resultant PMCs and the executed plurality of μBenchmarks; selecting a number of PMCs based upon their degree of correlation between the plurality of μBenchmarks to form a reduced PMC array.

The information processing circuit 10 performs operations on layers in deep learning, and includes a product sum circuit 11 which performs a product-sum operation using input data and parameter values, and a parameter value output circuit 12 which outputs the parameter values, wherein the parameter value output circuit 12 is composed of a combinational circuit, and includes a first parameter value output circuit 13 manufactured in a way that a circuit configuration cannot be changed and a second parameter value output circuit 14 manufactured in a way that allows a circuit configuration to be changed.

The information processing circuit 10 performs operations on layers in deep learning, and includes a product sum circuit 11 which performs a product-sum operation using input data and parameter values, and a parameter value output circuit 12 which outputs the parameter values, wherein the parameter value output circuit 12 is composed of a combinational circuit, and includes a first parameter value output circuit 13 manufactured in a way that a circuit configuration cannot be changed and a second parameter value output circuit 14 manufactured in a way that allows a circuit configuration to be changed.

Embodiments herein include detecting a transformation in a circuit layout before clock tree synthesis is performed, and in response, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit. Moreover, the embodiments includes determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit and adjusting the circuit layout based on the timing constraint to affect when the combinational logic generates the enable signal.