A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.

Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.

Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.

A method for dependent failure analysis of a circuit design includes obtaining a circuit design comprising a plurality of circuit elements, and generating a first cone of influence and a second cone of influence for the circuit design. The first cone of influence corresponds to a first one or more inputs of the circuit design. The second cone of influence corresponds to a second one or more inputs of the circuit design. The method further includes determining a first shared circuit element of the circuit elements within a first intersection between the first cone of influence and the second cone of influence. Further, the method includes determining a first coupling factor based on the first intersection between the first cone of influence and the second cone of influence, and outputting the first shared circuit element and the first coupling factor to a memory.

A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.

Embodiments herein include detecting a transformation in a circuit layout before clock tree synthesis is performed, and in response, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit. Moreover, the embodiments includes determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit and adjusting the circuit layout based on the timing constraint to affect when the combinational logic generates the enable signal.

Embodiments herein include detecting a transformation in a circuit layout before clock tree synthesis is performed, and in response, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit. Moreover, the embodiments includes determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit and adjusting the circuit layout based on the timing constraint to affect when the combinational logic generates the enable signal.

A power control semiconductor device includes: a voltage control transistor connected between an input terminal and an output terminal; a control circuit that controls the voltage control transistor in accordance with a voltage of the output terminal; and an external terminal that controls an output voltage externally. The control circuit includes: a first divider which has resistor elements connected in series to the output terminal and which divides the output voltage of the output terminal; a first error amplifier that outputs a voltage corresponding to a potential difference between a predetermined reference voltage and a voltage divided by the first divider; and an output voltage change circuit that changes the divided voltage in accordance with a voltage input to the external terminal to change the output voltage in accordance with the voltage of the external terminal.

A power control semiconductor device includes: a voltage control transistor connected between an input terminal and an output terminal; a control circuit that controls the voltage control transistor in accordance with a voltage of the output terminal; and an external terminal that controls an output voltage externally. The control circuit includes: a first divider which has resistor elements connected in series to the output terminal and which divides the output voltage of the output terminal; a first error amplifier that outputs a voltage corresponding to a potential difference between a predetermined reference voltage and a voltage divided by the first divider; and an output voltage change circuit that changes the divided voltage in accordance with a voltage input to the external terminal to change the output voltage in accordance with the voltage of the external terminal.

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a printed circuit board schematic and one or more electronic circuits. Embodiments may further include automatically generating, one or more circuit templates based upon, at least in part, the printed circuit board schematic and one or more electronic circuits. The one or more circuit templates may be stored at an electronic design database. Embodiments may also include receiving a current printed circuit board schematic and automatically determining whether a subcircuit of the current printed circuit board schematic is an exact or approximate match with the one or more circuit templates.