A chip aka integrated circuit, the chip comprising configuration register/s, typically volatile, and/or at least one on-chip non-volatile memory m typically including at least one reserved memory location, which may be reserved for storing contents of at least one typically volatile configuration register r, from among the configuration registers; and/or apparatus configured for, at least once, storing values which may be indicative of content of at least one typically volatile configuration register r from among the registers, e.g. in the on-chip non-volatile memory m, e.g. at the at least one reserved memory location.

A chip aka integrated circuit, the chip comprising configuration register/s, typically volatile, and/or at least one on-chip non-volatile memory m typically including at least one reserved memory location, which may be reserved for storing contents of at least one typically volatile configuration register r, from among the configuration registers; and/or apparatus configured for, at least once, storing values which may be indicative of content of at least one typically volatile configuration register r from among the registers, e.g. in the on-chip non-volatile memory m, e.g. at the at least one reserved memory location.

A repository is configured in a hybrid data processing environment comprising a classical computing system and a quantum computing system, to hold a plurality of quantum circuit components (QCC(s)). A degree of difficulty in simulating the received QCC in the classical computing system is transformed into a classical hardness score. A degree of difficulty in implementing the received QCC in the quantum computing system is transformed into a quantum hardness score. A first parameter in a metadata data structure associated with the received QCC is populated with the classical hardness score. A second parameter in the metadata data structure associated with the received QCC is populated with the quantum hardness score. The received QCC is transformed into a library element by at least augmenting the received QCC with the metadata data structure. The library element is added to the repository.

Methods, apparatus, and processor-readable storage media for an automated platform design tool are provided herein. An example method includes extracting information from a first file corresponding to a first computing design, the information including an identifier of at least one network, components associated with the identifier, and connections for each of the components; comparing the first computing design to a second computing design, wherein the comparing comprises: detecting that a second schematic file corresponding to the second computing design comprises the identifier, and determining, for at least one given component, whether the second schematic file includes a matching component based on the set of connections for the at least one given component; determining differences between the first computing design and the second computing design based on the results of the comparing; and initiating at least one automated action based at least in part on the one or more differences.

Methods, apparatus, and processor-readable storage media for an automated platform design tool are provided herein. An example method includes extracting information from a first file corresponding to a first computing design, the information including an identifier of at least one network, components associated with the identifier, and connections for each of the components; comparing the first computing design to a second computing design, wherein the comparing comprises: detecting that a second schematic file corresponding to the second computing design comprises the identifier, and determining, for at least one given component, whether the second schematic file includes a matching component based on the set of connections for the at least one given component; determining differences between the first computing design and the second computing design based on the results of the comparing; and initiating at least one automated action based at least in part on the one or more differences.

Creation of subsystems for a user design to be implemented in an integrated circuit (IC) includes generating, using computer hardware, a subsystem topology based on user provided subsystem data, wherein the subsystem topology specifies a plurality of subsystems of the user design where each subsystem includes a master circuit, and determining, using the computer hardware, a system management identifier for each master circuit of the subsystem topology. Programming data for programmable protection circuits of the IC can be automatically generated using the computer hardware based on the subsystem topology and system management identifiers. The programmable protection circuits, when programmed with the programming data, form the plurality of subsystems and physically isolate the plurality of subsystems on the integrated circuit from one another.

Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

A method of testing a change in a software code includes, searching a database of tests to identify a subset of the tests that include a function that executes the change, forming, from the subset, a multitude of groups each having a different execution path. The tests in the same group have the same execution path. The method further includes prioritizing the tests within each of the multitude of groups based on one or more testing characteristics, and selecting, from each of the groups, one or more of the prioritized tests to test the change.

Systems and methods for producing individualized processing chips, each individualized processing chip being arranged to carry out a common processing operation are disclosed. A processing chip design is received, wherein the common processing operation is specified, at least in part, by the processing chip design. For each individualized processing chip the processing chip design is individualized to produce an individualized processing chip design, in accordance with an individualized set of transformations for the individualized processing chip, by including a respective set of modifications as part of the individualized processing chip design that implement the individualized set of transformations. Each transformation of the individualized set of transformations is a transform for an interconnect, specified in the processing chip design, of at least two logic cells specified in the processing chip design. For each individualized processing chip the individualized processing chip design is provided for fabrication of the individualized processing chip according to the individualized processing chip design. The individualized set of transformations for one individualized chip is different to the individualized set of transformations for at least one other individualized chip.

Systems and methods for producing individualized processing chips, each individualized processing chip being arranged to carry out a common processing operation are disclosed. A processing chip design is received, wherein the common processing operation is specified, at least in part, by the processing chip design. For each individualized processing chip the processing chip design is individualized to produce an individualized processing chip design, in accordance with an individualized set of transformations for the individualized processing chip, by including a respective set of modifications as part of the individualized processing chip design that implement the individualized set of transformations. Each transformation of the individualized set of transformations is a transform for an interconnect, specified in the processing chip design, of at least two logic cells specified in the processing chip design. For each individualized processing chip the individualized processing chip design is provided for fabrication of the individualized processing chip according to the individualized processing chip design. The individualized set of transformations for one individualized chip is different to the individualized set of transformations for at least one other individualized chip.