Rebuilding a next compile-time Intellectual Property (IP) core can include determining an IP core included in a runtime design for an integrated circuit (IC) by evaluating metadata of the runtime design. The IP core specifies a circuit configured for implementation in programmable circuitry of the IC. Source code for the IP core may be retrieved automatically based on source data read from the metadata. A new instance of the IP core, including the source code, may be generated in a memory. The new instance of the IP core may be included within a new compile time design.

An integrated circuit system includes a temperature sensor circuit that generates an output indicative of a temperature in an integrated circuit. The integrated circuit system also includes a temperature management controller circuit that compares the temperature indicated by the output of the temperature sensor circuit to a temperature threshold. The integrated circuit system further includes temperature reduction circuitry and/or design compilation techniques and partial or full reconfiguration that controls the temperature in the integrated circuit system. The temperature management controller circuit causes the temperature reduction circuitry to reduce the temperature in response to the temperature indicated by the output of the temperature sensor circuit exceeding the temperature threshold. The temperature sensor circuit, the temperature management controller circuit, and the temperature reduction circuitry may be implemented by soft logic circuits, hard logic circuits, or any combination thereof.

An integrated circuit system includes a temperature sensor circuit that generates an output indicative of a temperature in an integrated circuit. The integrated circuit system also includes a temperature management controller circuit that compares the temperature indicated by the output of the temperature sensor circuit to a temperature threshold. The integrated circuit system further includes temperature reduction circuitry and/or design compilation techniques and partial or full reconfiguration that controls the temperature in the integrated circuit system. The temperature management controller circuit causes the temperature reduction circuitry to reduce the temperature in response to the temperature indicated by the output of the temperature sensor circuit exceeding the temperature threshold. The temperature sensor circuit, the temperature management controller circuit, and the temperature reduction circuitry may be implemented by soft logic circuits, hard logic circuits, or any combination thereof.

A system for optimizing scan pipelining may include a processor and a memory. The processor may generate and insert, based on prior analysis of the physical layout of the circuit, an optimized number of pipeline stages between a first block and a second block in a hardware test design, a first scan chain including at least one pipeline stage of a head pipeline stage or a tail pipeline stage. The processor may insert a plurality of flip-flops into the first scan chain. The processor may determine at least one clock to be used for the at least one pipeline stage, using the plurality of flip-flops so as to eliminate the need of a lockup element between the at least one pipeline stage and the plurality of flip-flops. The processor may generate, based on the at least one clock, a second scan chain that connects the at least one pipeline stage and the plurality of flip-flops.

A system for optimizing scan pipelining may include a processor and a memory. The processor may generate and insert, based on prior analysis of the physical layout of the circuit, an optimized number of pipeline stages between a first block and a second block in a hardware test design, a first scan chain including at least one pipeline stage of a head pipeline stage or a tail pipeline stage. The processor may insert a plurality of flip-flops into the first scan chain. The processor may determine at least one clock to be used for the at least one pipeline stage, using the plurality of flip-flops so as to eliminate the need of a lockup element between the at least one pipeline stage and the plurality of flip-flops. The processor may generate, based on the at least one clock, a second scan chain that connects the at least one pipeline stage and the plurality of flip-flops.

Disclosed herein is a method for making embryonic bio-inspired hardware efficient against faults through self-healing, fault prediction, and fault-prediction assisted self-healing. The disclosed self-healing recovers a faulty embryonic cell through innovative usage of healthy cells. Through experimentations, it is observed that self-healing is effective, but it takes a considerable amount of time for the hardware to recover from a fault that occurs suddenly without forewarning. To get over this problem of delay, novel deep learning-based formulations are utilized for fault predictions. The self-healing technique is then deployed along with the disclosed fault prediction methods to gauge the accuracy and delay of embryonic hardware.

A method for controlling a PCBA data distributed ledger located on blockchain network and a system for implementing the method are disclosed. The method may comprise scanning, by an optical label reader, an optical label located on a PCB and decoding, by an entity device, the optical label. The method may further include receiving, by a ledger controller, a request to access a distributed ledger from the entity device; verifying, by the blockchain nodes, a public key received from the entity device; determining, by the ledger controller, whether a private key received from the entity device matches a stored login credential; and determining whether to allow the entity device to access at least a first block on the distributed ledger.

A method for controlling a PCBA data distributed ledger located on blockchain network and a system for implementing the method are disclosed. The method may comprise scanning, by an optical label reader, an optical label located on a PCB and decoding, by an entity device, the optical label. The method may further include receiving, by a ledger controller, a request to access a distributed ledger from the entity device; verifying, by the blockchain nodes, a public key received from the entity device; determining, by the ledger controller, whether a private key received from the entity device matches a stored login credential; and determining whether to allow the entity device to access at least a first block on the distributed ledger.

A method and a system for recording an integrated circuit version are provided. The method is adapted to a register in an integrated circuit, which includes the following steps: recording the integrated circuit version with N bits, in which N is an integer greater than 1; and amending only a bit value of at least one bit selected from the N bits that have not been used for denoting any past integrated circuit version each time when the integrated circuit is revised.

A system determines physical design information along a logic hierarchy of a circuit design. The system accesses physical design metrics associated with different parts of a physical design of a circuit. The system accesses a logic design of the circuit comprising a hierarchy of logic blocks. The system determines the physical design metrics associated with one or more logic blocks of the hierarchy of the logic design based on a relation between the physical design and the logic design. The system configures a user interface to display the hierarchy of the logic design of the circuit along with the physical design metrics associated with the one or more logic blocks of the hierarchy. The system sends the configured user interface for display.