Fabricating a first semiconductor device cell using a first process based on a first process parameter or material comprises extracting semiconductor device parameters from the first process parameters to obtain extracted semiconductor device parameters of a first semiconductor device cell. The fabrication process includes training an artificial intelligence to obtain a predictive artificial intelligence using training data as input, the training data comprising the extracted semiconductor device cell parameters and the first process parameter or material. A proposed process modification is provided to the predictive artificial intelligence to generate a predicted cell delay by the predictive artificial intelligence. The predicted cell delay is evaluated against a cell delay threshold. When the predicted cell delay satisfies the cell delay threshold, a new semiconductor device cell is fabricated using a modified process incorporating the proposed process modification.

A system, and corresponding method, is described for using a model to predict the physical behavior of IP from an HDL representation of the IP. The system generated data for training and testing the model by treating the logical parameters and physical parameters subset as one for the IP block. The system digitizes the non-numerical parameters and compresses timing arcs. The system uses the trained model to predict performance, power, and area (PPA) behavior for an IP block directly from the combined vector of logical parameter values and physical parameter values.

A system, and corresponding method, is described for using a model to predict the physical behavior of IP from an HDL representation of the IP. The system generated data for training and testing the model by treating the logical parameters and physical parameters subset as one for the IP block. The system digitizes the non-numerical parameters and compresses timing arcs. The system uses the trained model to predict performance, power, and area (PPA) behavior for an IP block directly from the combined vector of logical parameter values and physical parameter values.

A method of selecting relative timing constraints for enforcing in an asynchronous circuit is presented. The method includes selecting one or more sets of relative timing constraints, which include a first set of relative timing constraints, wherein the first set of relative timing constraints meets the following criteria: i) the first set is suitable for preventing the asynchronous circuit from entering two or more bad states in which a correctness property of the asynchronous circuit is violated, and ii) the first set comprises a plurality of relative timing constraints, wherein each relative timing constraint within the first set is associated with a bad state whose associated relative timing constraints comprise this relative timing constraint but no other relative timing constraint that is implied by another relative timing constraint in the first set.

A method of selecting relative timing constraints for enforcing in an asynchronous circuit is presented. The method includes selecting one or more sets of relative timing constraints, which include a first set of relative timing constraints, wherein the first set of relative timing constraints meets the following criteria: i) the first set is suitable for preventing the asynchronous circuit from entering two or more bad states in which a correctness property of the asynchronous circuit is violated, and ii) the first set comprises a plurality of relative timing constraints, wherein each relative timing constraint within the first set is associated with a bad state whose associated relative timing constraints comprise this relative timing constraint but no other relative timing constraint that is implied by another relative timing constraint in the first set.

A system, method, apparatus and integrated circuit are provided for collecting runtime performance data with a set of hardware timers under control of a dedicated hardware control register by connecting a central processing unit (CPU) and memory to a timer block bank having a plurality of timer instances which are selectively enabled and activated to collect runtime performance data during execution of application code by measuring specified software execution events, where the dedicated hardware control register includes a plurality of register fields for independently controlling activation behavior of the plurality of timer instances in response to a single write operation to all register fields in the hardware control register.

A new low-power test compression method and design for testability (DFT) architecture are proposed for deterministic test pairs for launch-on-capture (LOC) transition fault testing by using a new seed encoding scheme, a new low-power test application procedure and a new test compression architecture. The new seed encoding scheme generates seeds for all test pairs by selecting a primitive polynomial that encodes all test pairs of a compact test set. The low-power test compression architecture includes: (1) the LFSR established by the selected primitive polynomial and the selected number of extra variables injected to the LFSR; (2) the scan tree architecture for LOC transition fault testing; and (3) the new gating technique. A new static test compaction scheme is proposed by bitwise modifying the values of a seed and the extra variables. A new technique for test point insertion is proposed for LOC delay testing in the two-frame-circuit model, which apparently reduces test data volume.

A new low-power test compression method and design for testability (DFT) architecture are proposed for deterministic test pairs for launch-on-capture (LOC) transition fault testing by using a new seed encoding scheme, a new low-power test application procedure and a new test compression architecture. The new seed encoding scheme generates seeds for all test pairs by selecting a primitive polynomial that encodes all test pairs of a compact test set. The low-power test compression architecture includes: (1) the LFSR established by the selected primitive polynomial and the selected number of extra variables injected to the LFSR; (2) the scan tree architecture for LOC transition fault testing; and (3) the new gating technique. A new static test compaction scheme is proposed by bitwise modifying the values of a seed and the extra variables. A new technique for test point insertion is proposed for LOC delay testing in the two-frame-circuit model, which apparently reduces test data volume.

The disclosure relates to a method, computer program product or data processing system for performing graph-based static timing analysis, GBA, of an integrated circuit design having a set of timing paths. The method comprises identifying a subset of the set of timing paths and performing path-based analysis, PBA, of the subset of timing paths to determine at least one PBA timing parameter for each timing path of the subset of timing paths. The method further comprises determining at least one optimized GBA timing parameter for at least one timing path of the subset of timing paths by minimizing a function that is based on a difference between the at least one optimized GBA timing parameter and the at least one PBA timing parameter of the at least one timing path.

The disclosure relates to a method, computer program product or data processing system for performing graph-based static timing analysis, GBA, of an integrated circuit design having a set of timing paths. The method comprises identifying a subset of the set of timing paths and performing path-based analysis, PBA, of the subset of timing paths to determine at least one PBA timing parameter for each timing path of the subset of timing paths. The method further comprises determining at least one optimized GBA timing parameter for at least one timing path of the subset of timing paths by minimizing a function that is based on a difference between the at least one optimized GBA timing parameter and the at least one PBA timing parameter of the at least one timing path.