A specialized low drop-out voltage regulator (LDO) computer system stores a generalized base model of an LDO. The base model includes values representing a circuit topology and a set of analog behavior blocks associated with the generalized LDO. Values of a set of operational parameters associated with a specific model of LDO are input to the specialized LDO computer system from a data sheet associated with the specific model of LDO. The specialized LDO computer system transforms the set of operational parameters into a computer model of the specific LDO. The LDO-specific computer model is output as a netlist or as a set of instantiation control values to control external hardware such as an integrated circuit die tooling system or a computer graphical display system.

A system and method for compensating signal delay across a solid state photomultiplier. The method including determining respective arrival times of signals from a plurality of microcells of the photomultiplier, calculating a signal transit time delay difference between the respective arrival times for individual signals, correlating the individual transit time delay differences to an amount of respective signal propagation compensation for respective microcells of the photomultiplier, and introducing the respective signal propagation compensation into circuitry of the respective microcells. The method also includes at least one of adjusting a response shape of a photodiode within each of the plurality of microcells, adjusting operating parameters of a one-shot pulse circuit within the microcells, and modifying circuit design values of each microcells during fabrication of the photomultiplier. A non-transitory computer readable medium and a system for implementing the method on a row, column, and/or individual microcell level are disclosed.

An analog-function description creation apparatus is provided with a design table generator to generate a design table to describe parameter information to be used in an analog-function description model to be designed, variable information specifiable by a user arbitrarily, input port information including a name of at least one input port, output port information including a name of at least one output port, and condition information from the input port to the output port, and an analog-function description creator to create the analog-function description model corresponding to the design table.

A method and apparatus for providing power stably for direct current loads. A regulated transformer rectifier unit is controlled to provide regulated direct current power for the direct current loads at an output of the regulated transformer rectifier unit from alternating current power provided by an alternating current power source to an input of the regulated transformer rectifier unit. The direct current loads comprise passive direct current loads and active direct current loads comprising active switching power supplies. The direct current loads have at least one of constant power characteristics, resistive power characteristics, inductive power characteristics, and capacitive power characteristics. A source impedance at the output of the regulated transformer rectifier unit is determined based on an aggregate load impedance of the direct current loads and stability criterion.

A high-ohmic circuit includes a plurality of high-ohmic branches coupled in parallel between a first node and a second node. Each of the plurality of high-ohmic branches includes a first plurality of series connected resistive elements forming a first series path from the first node to the second node, each of the first plurality of series connected resistive elements comprising a first diode-connected transistor. Each of the plurality of high-ohmic branches further includes a second plurality of series connected resistive elements forming a second series path from the first node to the second node, each of the second plurality of series connected resistive elements comprising a second diode-connected transistor. The high-ohmic circuit further includes a plurality of switches, each of the switches being coupled between a corresponding one of the plurality of high-ohmic branches and the second node.

Provided is a method for simulating electricity of a wafer chip. The method includes: a database is constructed, the database including spectroscopic data of a semiconductor structure of the wafer chip obtained from a target key process, actual electrical data of the wafer chip, and a correspondence between the spectroscopic data and the actual electrical data; the target key process is performed on a target wafer chip to obtain the spectroscopic data of the semiconductor structure of the target wafer chip obtained from the target key process, the spectroscopic data being target spectroscopic data; the electrical data of the target wafer chip is simulated based on the obtained target spectroscopic data and the database, the electrical data being target electrical data.

Provided is a method for simulating electricity of a wafer chip. The method includes: a database is constructed, the database including spectroscopic data of a semiconductor structure of the wafer chip obtained from a target key process, actual electrical data of the wafer chip, and a correspondence between the spectroscopic data and the actual electrical data; the target key process is performed on a target wafer chip to obtain the spectroscopic data of the semiconductor structure of the target wafer chip obtained from the target key process, the spectroscopic data being target spectroscopic data; the electrical data of the target wafer chip is simulated based on the obtained target spectroscopic data and the database, the electrical data being target electrical data.

A jumper cap circuit and a method for designing the same are provided. The jumper cap circuit includes: a three-pin header, a chip, a pull-up resistor or a pull-down resistor, and a resistor R1. The header is connected to the chip via the pull-up resistor or the pull-down resistor, and a voltage dividing circuit is constituted by the resistor R1 and the pull-up resistor or the pull-down resistor, and the resistor R1 is connected to a pin of the pin header. The method includes: acquiring a default input state of a chip, and setting, based on the default input state of the chip, a default value of the chip by arranging a first resistor in a path where a first pin of the three-pin header is located and arranging a second resistor in a path where a second pin of the three-pin header is located.

A jumper cap circuit and a method for designing the same are provided. The jumper cap circuit includes: a three-pin header, a chip, a pull-up resistor or a pull-down resistor, and a resistor R1. The header is connected to the chip via the pull-up resistor or the pull-down resistor, and a voltage dividing circuit is constituted by the resistor R1 and the pull-up resistor or the pull-down resistor, and the resistor R1 is connected to a pin of the pin header. The method includes: acquiring a default input state of a chip, and setting, based on the default input state of the chip, a default value of the chip by arranging a first resistor in a path where a first pin of the three-pin header is located and arranging a second resistor in a path where a second pin of the three-pin header is located.

A chip includes a pad and a driver having an output coupled to the pad. The chip also includes one or more diodes coupled between the pad and a ground bus, wherein the one or more diodes are in a forward direction from the pad to the ground bus.