A function equivalence check method includes receiving a cell list, receiving an analog constraint of a cell in the cell list, generating the full-coverage input stimuli according to the analog constraint, performing a behavioral-level simulation using the full-coverage input stimuli and according to the behavioral code to generate a behavioral-level simulation result, performing a circuit-level simulation using the full-coverage input stimuli and according to the circuit-level netlist to generate a circuit-level simulation result, and comparing the behavioral-level simulation result and the circuit-level simulation result to generate a comparison report for an analog value auto-comparison.

A function equivalence check method includes receiving a cell list, receiving an analog constraint of a cell in the cell list, generating the full-coverage input stimuli according to the analog constraint, performing a behavioral-level simulation using the full-coverage input stimuli and according to the behavioral code to generate a behavioral-level simulation result, performing a circuit-level simulation using the full-coverage input stimuli and according to the circuit-level netlist to generate a circuit-level simulation result, and comparing the behavioral-level simulation result and the circuit-level simulation result to generate a comparison report for an analog value auto-comparison.

Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

A system, method, and apparatus for analog/mixed-signal defect simulation and analysis methodology. Block-level behavioral models simulated at transistor level, using automated or manual techniques, are binned for all the possible defects that have similar results. A likelihood of a given block-level behavioral model is determined from the likelihood of the defects it represents. Deliberate binning in another embodiment is based on one or more functions of the given block being simulated, e.g., by amplifier gain for an analog amplifier, or by speed/power for a digital part. One or more bins are ‘defect-free behavior’ that cover nominal and corner behavior (power & timing), from manufacturing variability, which may be labeled as “failed” or “degraded” depending on specific performances. For standard parts, test-benches provide the binning from the block-level behavioral models as a result.

A system, method, and apparatus for analog/mixed-signal defect simulation and analysis methodology. Block-level behavioral models simulated at transistor level, using automated or manual techniques, are binned for all the possible defects that have similar results. A likelihood of a given block-level behavioral model is determined from the likelihood of the defects it represents. Deliberate binning in another embodiment is based on one or more functions of the given block being simulated, e.g., by amplifier gain for an analog amplifier, or by speed/power for a digital part. One or more bins are ‘defect-free behavior’ that cover nominal and corner behavior (power & timing), from manufacturing variability, which may be labeled as “failed” or “degraded” depending on specific performances. For standard parts, test-benches provide the binning from the block-level behavioral models as a result.

A computing system implementing a design verification system can classify a mixed-signal circuit design describing an electronic device based on a design topology of the mixed-signal circuit design. This classification can be performed by identifying a top-level design block in the mixed-signal circuit design, traversing a connectivity of a design hierarchy to identify lower-level design blocks in the mixed-signal circuit design, and classifying the mixed-signal circuit design based on at least one of a design type of the top-level design block, design types of the lower-level design blocks, or a connectivity of design blocks in the mixed-signal circuit design. The design verification system can selectively partition the mixed-signal circuit design into an analog partition and a digital partition based on the classification, and simulate the analog partition of the mixed-signal circuit design with an analog simulator and the digital partition of the mixed-signal circuit design with a digital simulator.

A computing system implementing a design verification system can classify a mixed-signal circuit design describing an electronic device based on a design topology of the mixed-signal circuit design. This classification can be performed by identifying a top-level design block in the mixed-signal circuit design, traversing a connectivity of a design hierarchy to identify lower-level design blocks in the mixed-signal circuit design, and classifying the mixed-signal circuit design based on at least one of a design type of the top-level design block, design types of the lower-level design blocks, or a connectivity of design blocks in the mixed-signal circuit design. The design verification system can selectively partition the mixed-signal circuit design into an analog partition and a digital partition based on the classification, and simulate the analog partition of the mixed-signal circuit design with an analog simulator and the digital partition of the mixed-signal circuit design with a digital simulator.

Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.