G06F2205/123

Method and system for implementing lock free shared memory with single writer and multiple readers
10235292 · 2019-03-19 · ·

A method and a system for implementing a lock-free shared memory accessible by a plurality of readers and a single writer are provided herein. The method including: maintaining a memory accessible by the readers and the writer, wherein the memory is a hash table having at least one linked list of buckets, each bucket in the linked list having: a bucket ID, a pointer to an object, and a pointer to another bucket; calculating a pointer to one bucket of the linked list of buckets based on a hash function in response to a read request by any of the readers; and traversing the linked list of buckets, to read a series of objects corresponding with the traversed buckets, while checking that the writer has not: added, amended, or deleted objects pointed to by any of said traversed buckets, wherein said checking is carried out in a single atomic action.

METHOD FOR CYCLE ACCURATE DATA TRANSFER IN A SKEWED SYNCHRONOUS CLOCK DOMAIN
20190004564 · 2019-01-03 ·

A method and system for cycle accurate data transfer between skewed source synchronous clocks is envisaged. The procedure starts through reset. On reset, both the write and read address registers are set to point to location 0. Source clock is stopped to disable active clock edges to both write and read address registers during the reset procedure. The source clock is subsequently started to deliver active edges w both write and read address registers. On every active source clock edge, data is pushed into the data register based on the location pointed by write address resister. On every skewed active clock edge, data is read from the data register based on the address pointed by read address register. Due to the delayed nature of clock reaching the read address register, write address register increments first and stores data into the data register.

TRANSITIONING A BUFFER TO BE ACCESSED EXCLUSIVELY BY A DRIVER LAYER FOR WRITING IMMEDIATE DATA STREAM

Example method includes: negotiating, with a client device, a number of simultaneous I/O commands allowed in a single session between a storage device and the client device; pre-allocating a number of immediate data buffers for the single session based on the negotiated number of simultaneous I/O commands; receiving a write I/O command with immediate data, wherein the immediate data is transmitted within a single PDU as the I/O command; transitioning the pre-allocated buffers from a network interface state to a driver state in an atomic operation, the driver state enabling the pre-allocated buffers to be accessed by a driver layer of the storage device exclusively, and the atomic operation preventing other I/O commands from transitioning the network interface state of the pre-allocated buffers until the atomic operation is completed; and writing the immediate data to the pre-allocated buffers that are in the driver state.

Compile time logic for inserting a buffer between a producer operation unit and a consumer operation unit in a dataflow graph

A dataflow graph for an application has operation units that are configured to be producers and consumers of tensors. A write access pattern of a particular producer specifies an order in which the particular producer generates elements of a tensor, and a read access pattern of a corresponding consumer specifies an order in which the corresponding consumer processes the elements of the tensor. The technology disclosed detects conflicts between the producers and the corresponding consumers that have mismatches between the write access patterns and the read access patterns. A conflict occurs when the order in which the particular producer generates the elements of the tensor is different from the order in which the corresponding consumer processes the elements of the tensor. The technology disclosed resolves the conflicts by inserting buffers between the producers and the corresponding consumers.

Data transfer apparatus and data transfer method
09703731 · 2017-07-11 · ·

In a data transfer apparatus, a data coupling unit includes a command transfer unit that outputs a write address based on transfer requests input from a bus master, a judgment result indicating whether data corresponding to the input transfer requests are continues, and a judgment result indicating whether a size after coupling exceeds an arbitrary burst length. The data coupling unit includes a buffer unit that retains the data input from the bus master according to the write address, a buffer management unit that retains information used by the data coupling unit to couple the transfer requests, and a coupled command transfer unit that generates a transfer request after coupling, having a data size less than or equal to the arbitrary burst length and a start address based on the arbitrary burst length.

Determining conditions associated with accessing data stores

A device may receive, from a user, a selection of one of a graphical representation of a data store included in a model or a string of text that identifies a variable associated with the model. The device may provide, based on the selection, a user interface for providing pattern information associated with the data store. The device may receive, via the user interface, the pattern information associated with the data store. The pattern information may identify one or more elements included in the model and a pattern associated with the one or more elements accessing the data store during an execution of the model. The device may analyze the model based on the pattern information and may output a result. The result may indicate whether the model accesses the data store in compliance with the pattern.