A wireless control device includes a power source, one or more sensors, one or more switches, a wireless transceiver circuit, an antenna connected to the wireless transceiver circuit, and a processor communicably coupled to the power source, the one or more sensors, the one or more switches, and the wireless transceiver circuit. The processor receives a data from the one or more sensors or the one or more switches, determines a pre-defined action associated with the data that identifies one or more external devices and one or more tasks, and transmits one or more control signals via the wireless transceiver circuit and the antenna that instruct the identified external device(s) to perform the identified task(s).

Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.

A wireless control device includes a power source, one or more sensors, one or more switches, a wireless transceiver circuit, an antenna connected to the wireless transceiver circuit, and a processor communicably coupled to the power source, the one or more sensors, the one or more switches, and the wireless transceiver circuit. The processor receives a data from the one or more sensors or the one or more switches, determines a pre-defined action associated with the data that identifies one or more external devices and one or more tasks, and transmits one or more control signals via the wireless transceiver circuit and the antenna that instruct the identified external device(s) to perform the identified task(s).

A wireless control device includes a power source, one or more sensors, one or more switches, a wireless transceiver circuit, an antenna connected to the wireless transceiver circuit, and a processor communicably coupled to the power source, the one or more sensors, the one or more switches, and the wireless transceiver circuit. The processor receives a data from the one or more sensors or the one or more switches, determines a pre-defined action associated with the data that identifies one or more external devices and one or more tasks, and transmits one or more control signals via the wireless transceiver circuit and the antenna that instruct the identified external device(s) to perform the identified task(s).

A processor applies offset values to read and write pointers to a first-in-first-out buffer (FIFO) for data being transferred between clock domains. The pointer offsets are based on a frequency ratio between the clock domains, and reduce latency while ensuring that data is not read by the receiving clock domain from an entry of the FIFO until after the data has been written to the entry, thereby reducing data transfer errors. The processor resets the pointer offset values in response to a change in clock frequency at one or both of the clock domains, allowing the processor to continue to accurately transfer data in response to clock frequency changes.

An FPGA-based interface signal remapping method, relates to the technical field of nuclear power system, and solves the technical problems of poor reliability, readability and debuggability in the prior art. The method comprises dividing an internal programmable logic of an FPGA chip into two independent modules, with one module being an I/O module and the other module being a Core module, using the I/O module to process signal excursion occurring when an external signal is input to or output from the FPGA chip, signal collision caused by line multiplexing, metastable state in a data transmission process, and a data transmission error between asynchronous clock domains, using the Core module to implement logical processing and computing; and introducing a master clock signal outside the FPGA chip into the FPGA chip through a global clock pin of the FPGA chip. The method provided in the invention is suitable for a nuclear power protection system platform.

Example method includes: negotiating, with a client device, a number of simultaneous I/O commands allowed in a single session between a storage device and the client device; pre-allocating a number of immediate data buffers for the single session based on the negotiated number of simultaneous I/O commands; receiving a write I/O command with immediate data, wherein the immediate data is transmitted within a single PDU as the I/O command; transitioning the pre-allocated buffers from a network interface state to a driver state in an atomic operation, the driver state enabling the pre-allocated buffers to be accessed by a driver layer of the storage device exclusively, and the atomic operation preventing other I/O commands from transitioning the network interface state of the pre-allocated buffers until the atomic operation is completed; and writing the immediate data to the pre-allocated buffers that are in the driver state.

A thread executed by a server to service events received into a deferred event buffer through connections to client sockets on client terminals, acquires a buffer lock responsive to the buffer lock not being acquired by another thread, and increments a buffer iteration counter. The thread identifies buffer entry N as a next candidate entry, and determines if two preconditions are satisfied: 1) a connection lock of a connection X context structure associated with the buffer entry N is not acquired by another thread; and 2) a connection iteration counter of the connection X context is less than the buffer iteration counter. Responsive to both preconditions being satisfied, the thread acquires a connection lock of the connection X context structure, removes the buffer entry N, and releases the buffer lock. The connection lock is released responsive to completing execution of a callback function performing the buffer entry N.

A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.

Transaction handling apparatus comprises a response buffer; and tracking circuitry to store data defining each transaction issued by one or more transaction master devices and to control routing of a transaction response to a given transaction either to the response buffer or as an output to the transaction master device which issued the given transaction; the response buffer being configured to access an indicator for each buffered transaction response indicating whether a response has been output by the apparatus for a previously issued transaction, on which that buffered transaction response depends, and to output the buffered transaction response to the transaction master device which issued that transaction when the previously issued transaction has already been output by the apparatus.