Patent classifications
G06F2206/1004
Configurable I/O address translation data structure
In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.
Cooperative physical defragmentation by a file system and a storage device
A storage system includes a host including a processor and a storage device including a controller and a flash memory unit. The host is configured to read physically fragmented data of a file stored in one or more physical storage regions of the flash memory unit and write the data continuously into other one or more physical regions of the flash memory unit, such that the data are physically defragmented.
Optimized record placement in graph database
Methods and systems are disclosed for optimizing record placement in a graph by minimizing fragmentation when writing data. Issues with fragmented data within a graph database are addressed on the record level by placing data that is frequently accessed together contiguously within memory. For example, a dynamic rule set may be developed based on dynamically analyzing access patterns of the graph database, policies, system characteristics and/or other heuristics. Based on statistics regarding normal query patterns, the systems and methods may identify an optimal position for certain types of edges that are often traversed with respect to particular types of nodes.
OPTIMIZED RECORD PLACEMENT IN GRAPH DATABASE
Methods and systems are disclosed for optimizing record placement in a graph by minimizing fragmentation when writing data. Issues with fragmented data within a graph database are addressed on the record level by placing data that is frequently accessed together contiguously within memory. For example, a dynamic rule set may be developed based on dynamically analyzing access patterns of the graph database, policies, system characteristics and/or other heuristics. Based on statistics regarding normal query patterns, the systems and methods may identify an optimal position for certain types of edges that are often traversed with respect to particular types of nodes.
Defragmentation of persistent main memory
Disclosed herein are system, method, and computer program product embodiments for defragmentation of persistent main memory (e.g., storage class memory). An embodiment operates by determining that a request to allocate a block of persistent main memory cannot be fulfilled, identifying the largest block of a plurality of free blocks associated with a persistent allocator, and punching a hole at the location of the block within a segment of the persistent main memory. The embodiment further operates by determining that at least one neighboring block of the largest block is also a hole, and coalescing the at least one neighboring block and the largest block.
DEFRAGMENTATION OF PERSISTENT MAIN MEMORY
Disclosed herein are system, method, and computer program product embodiments for defragmentation of persistent main memory (e.g., storage class memory). An embodiment operates by determining that a request to allocate a block of persistent main memory cannot be fulfilled, identifying the largest block of a plurality of free blocks associated with a persistent allocator, and punching a hole at the location of the block within a segment of the persistent main memory. The embodiment further operates by determining that at least one neighboring block of the largest block is also a hole, and coalescing the at least one neighboring block and the largest block.
Using storage defragmentation function to facilitate system checkpoint
A computer-implemented method is provided for a storage system comprising a processor in operable communication with a storage device that is configured into a plurality of respective regions of storage space. A first defragmentation process is performed on at least a first region of the plurality of respective regions of storage space to free a first portion of storage space in the a respective first region, where the freed first portion is reserved for user data and metadata associated with I/O requests to the storage system that are generated during a first operation running on the storage system. The storage system is configured to ensure that, during the first operation, user data and metadata are routed towards the first freed portion and kept separate from a set of system checkpoint information, associated with a first state of the storage system, stored in a protected portion of storage space.
Garbage collection in a distributed storage system
The presently disclosed subject matter includes various inventive aspects, which are directed for enabling execution of garbage collection process in a distributed storage-system.
DE-CENTRALIZED LOAD-BALANCING AT PROCESSORS
A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.
MEMORY SYSTEM AND METHOD
A memory system (100) includes a memory (2) including a plurality of pages (21) on each of which data can be arranged and a defragmenting device (4) that rearranges the data arranged on the plurality of pages (21). The memory (2) includes a plurality of tiles (22) each including one or more pages. Each of the plurality of tiles (22) is configured to be capable of transitioning among a plurality of states in which power consumption suppression rates are different. The plurality of states include a low power consumption state different from a power-off state. The defragmenting device (4) rearranges the data such that the tile (22) in which high access frequency data are collected and the tile (22) in which low access frequency data are collected are present.