An adder includes a primary carry bit generation circuit and a summing circuit. The primary carry bit generation circuit is configured to generate first carry bits for a first number of pairs of bits from first and second operands, and to generate second carry bits for a second number of pairs of bits from the first and second operands. The second number of pairs being different than the first number of pairs. The summing circuit is configured to generate first sums by adding bits of pairs from the first and second number of pairs and the first and second carry bits. The summing circuit is configured to generate second sums by adding bits of other pairs of the bits from first and second operands than the pairs in the first and second number of pairs and additional carry bits generated when adding the bits of the other pairs.

Disclosed is a parallel prefix adder structure with a carry bit generation circuit that generates primary carry bits for only some bit pairs and a sum circuit with ripple carry adders that use these primary carry bits to generate secondary carry bits and sum bits for a final sum. The carry bit generation circuit has different sections, which process different sequential sets of bit pairs and which have different sparsity configurations. As a result, generation of the primary carry bits is non-uniform. That is, in the different sections the primary carry bits are generated at different carry bit-to-bit pair ratios (e.g., the carry bit-to-bit pair ratios for the different sections can be 1:2, 1:4, and 1:2, respectively). For optimal performance, the specific bit pairs for which these primary carry bits are generated varies depending upon whether the maximum operand size is an odd number of bits or an even number.

Disclosed is a parallel prefix adder structure with a carry bit generation circuit that generates primary carry bits for only some bit pairs and a sum circuit with ripple carry adders that use these primary carry bits to generate secondary carry bits and sum bits for a final sum. The carry bit generation circuit has different sections, which process different sequential sets of bit pairs and which have different sparsity configurations. As a result, generation of the primary carry bits is non-uniform. That is, in the different sections the primary carry bits are generated at different carry bit-to-bit pair ratios (e.g., the carry bit-to-bit pair ratios for the different sections can be 1:2, 1:4, and 1:2, respectively). For optimal performance, the specific bit pairs for which these primary carry bits are generated varies depending upon whether the maximum operand size is an odd number of bits or an even number.

A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-1 of the K inputs.

A system includes an associative memory array and a concurrent adder. The memory array includes a plurality of sections, where each section includes cells arranged in rows and columns. The memory array stores bit j from a first multi-bit number and bit j from a second multi-bit number in a same column in section j. The concurrent adder performs, in parallel, multi-bit add operations of P pairs of multi-bit operands stored in columns of a memory array. Each pair of the P pairs is stored in a different column of the array and each add operation occurs in its associated different column.

The present disclosure relates generally to techniques for enhancing adders implemented on an integrated circuit. In particular, arithmetic performed by an adder implemented to receive operands having a first precision may be restructured so that a set of sub-adders may perform the arithmetic on a respective segment of the operands. More specifically, the adder may be restructured so that a sub-adder of the set of sub-adders may concurrently output a generate signal and a propagate signal, which may both be routed to a prefix network. The prefix network may determine respective carry bit(s), which may carry into and/or select a sum at a subsequent sub-adder of the restructured adder. As a result, the integrated circuit may benefit from increased efficiencies, reduced latency, and reduced resource consumption (e.g., area and/or power) involved with implementing addition, which may improve operations such as encryption or machine learning on the integrated circuit.

An integrated circuit that includes very large adder circuitry is provided. The very large adder circuitry receives more than two inputs each of which has hundreds or thousands of bits. The very large adder circuitry includes multiple adder nodes arranged in a tree-like network. The adder nodes divide the input operands into segments, computes the sum for each segment, and computes the carry for each segment independently from the segment sums. The carries at each level in the tree are accumulated using population counters. After the last node in the tree, the segment sums can then be combined with the carries to determine the final sum output. An adder tree network implemented in this way asymptotically approaches the area and performance latency as an adder network that uses infinite speed ripple carry adders.

A multi-bit adder apparatus comprising: a full adder stage configured to receive at least some of a plurality of least significant bits (LSBs) of first data and second data; and a half adder stage configured to receive at least some of a plurality of most significant bits (MSBs) of the first data and the second data; a carry generation stage coupled to the full adder stage and the half adder stage, wherein the carry generation stage includes at least one serial propagate-generate (PG) component; and a post summing stage coupled to the carry generation stage and the half adder stage and configured to generate a partial sum output of the first data and the second data, wherein a number of the at least some of the plurality of LSBs is different from a number of the at least some of the plurality of MSBs.

A system includes a non-destructive associative memory array and a predictor, a selector and a summer. The memory array includes a plurality of sections, each section includes cells arranged in rows and columns, to store bit j from a first multi-bit number and bit j from a second multi-bit number in a same column in section j. The predictor generally concurrently predicts a plurality of carry out values in each of the sections and the selector selects one of the predicted carry out values for all bits. The summer generally concurrently, for all bits, calculates a sum of the multi-bit numbers using the selected carry-out values.

The present disclosure relates generally to techniques for enhancing adders implemented on an integrated circuit. In particular, arithmetic performed by an adder implemented to receive operands having a first precision may be restructured so that a set of sub-adders may perform the arithmetic on a respective segment of the operands. More specifically, the adder may be restructured so that a decoder may determine a generate signal and a propagate signal for each of the sub-adders and may route the generate signal and the propagate signal to a prefix network. The prefix network may determine respective carry bit(s), which may carry into and/or select a sum at a subsequent sub-adder. As a result, the integrated circuit may benefit from increased efficiencies, reduced latency, and reduced resource consumption (e.g., area and/or power) involved with implementing addition, which may improve operations such as encryption or machine learning on the integrated circuit.