Control circuitry coupled to a multiply unit which includes a plurality of stage, each of which may be configured to perform a corresponding arithmetic function, may be configured to retrieve a given entry from a lookup table dependent upon a first portion of a binary representation of an input operand. An error value of an error function evaluated dependent upon a lookup value in a given entry of the plurality of entries is included in a predetermined error range. The control circuitry may be further configured to determine an initial approximation of a result of an iterative arithmetic operation using the first entry and initiate the iterative arithmetic operation using the initial approximation and the input operand.

A division operation apparatus is provided. The division operation apparatus includes a memory, a non-zero bit detection circuit, a mapping calculation circuit, a look-up circuit, a compensation circuit and a multiplication circuit. The memory stores a divisor look-up table including a plurality of entries. The non-zero bit detection circuit detects a number of a highest non-zero bit of the divisor. The mapping calculation circuit generates a mapped value of the divisor within a range of the divisor look-up table according to a mapping function. The look-up circuit retrieves a corresponding entry having a stored reciprocal according to the mapped value. The compensation circuit generates a compensation value according to the mapping function. The multiplication circuit multiplies a dividend, the stored reciprocal and the compensation value to generate a divided result of the dividend and the divisor.

A division operation apparatus is provided. The division operation apparatus includes a memory, a non-zero bit detection circuit, a mapping calculation circuit, a look-up circuit, a compensation circuit and a multiplication circuit. The memory stores a divisor look-up table including a plurality of entries. The non-zero bit detection circuit detects a number of a highest non-zero bit of the divisor. The mapping calculation circuit generates a mapped value of the divisor within a range of the divisor look-up table according to a mapping function. The look-up circuit retrieves a corresponding entry having a stored reciprocal according to the mapped value. The compensation circuit generates a compensation value according to the mapping function. The multiplication circuit multiplies a dividend, the stored reciprocal and the compensation value to generate a divided result of the dividend and the divisor.