Provided is a fast divider including an initial parameter setting unit and an arithmetic unit. The arithmetic unit is coupled to the initial parameter setting unit that receives a divisor and a dividend, and sets a plurality of initial parameters of a sequence according to the divisor and the dividend. The plurality of initial parameters includes an initial term, a first term and a common ratio having an absolute value smaller than 1. The arithmetic unit stores a recurrence relation of the sequence and iteratively computes a quotient using the recurrence relation according to the plurality of initial parameters. The recurrence relation indicates that a (k+1).sup.th term is equal to a product of a k.sup.th term multiplied by a sum of the common ratio and 1 subtracted by a product of a (k1).sup.th term multiplied by the common ratio. k is an integer larger than or equal to 1.

Systems, apparatuses, and methods for performing a division operation are disclosed. In one embodiment, a processor includes at least one arithmetic logic unit and a register file. In response to detecting a request to perform a division operation between a dividend and a divisor, the processor generates an initial approximation of the reciprocal of the divisor. Then, the processor converts the initial approximation of the reciprocal of the divisor into a fractional fixed point representation. The processor also introduces a small error into the initial approximation of the reciprocal of the divisor. Then, the processor implements one or more Newton-Raphson iterations for refining the approximation of the reciprocal and then multiplies the final reciprocal value by the dividend to generate the quotient.

The disclosed embodiments relate to the design of an integer division circuit, which comprises: a dividend-input that receives an integer dividend A; a divisor-input that receives an integer divisor B; a quotient-output that outputs an integer quotient q; and a division engine that executes the Goldschmidt method to divide A by B to produce q. During a pre-processing operation, which commences executing before the Goldschmidt method starts executing, the division engine determines whether A<B. If A<B, the division engine sets q=0 without having to execute the Goldschmidt method.

Systems, apparatuses, and methods for performing a division operation are disclosed. In one embodiment, a processor includes at least one arithmetic logic unit and a register file. In response to detecting a request to perform a division operation between a dividend and a divisor, the processor generates an initial approximation of the reciprocal of the divisor. Then, the processor converts the initial approximation of the reciprocal of the divisor into a fractional fixed point representation. The processor also introduces a small error into the initial approximation of the reciprocal of the divisor. Then, the processor implements one or more Newton-Raphson iterations for refining the approximation of the reciprocal and then multiplies the final reciprocal value by the dividend to generate the quotient.

Embodiments of a multiplier unit that may be used for division and square root operations are disclosed. The embodiments may provide a reduced and fixed latency for denormalization and rounding used in the division and square root operations. A storage circuit may be configured to receive first and second source operands. A multiplier circuit may be configured to perform a plurality of multiplication operations dependent upon the first and second source operands. Each result after an initial result of the multiplier may also depend on at least one previous result. Circuitry may be configured to perform a shift operation and a rounding operation on a given result of the plurality of results. An error of the given result may be less than a predetermined threshold value.

A method and computer system are provided for implementing a square root operation using an iterative converging approximation technique. The method includes fewer computations than conventional methods, and only includes computations which are simple to implement in hardware on a computer system, such as multiplication, addition, subtraction and shifting. Therefore, the methods described herein are adapted specifically for being performed on a computer system, e.g. in hardware, and allow the computer system to perform a square root operation with low latency and with low power consumption.