An oscillator circuit includes a plurality of inverters connected in a cascade, at least first and second feedback taps, and alternation circuitry. The at least first and second feedback taps are configured to feed-back at least respective first and second output signals taken from at least respective first and second points in the cascade. The alternation circuitry is configured to derive an input signal from at least the first and second output signals by alternating between at least the first and second feedback taps, and to apply the input signal to an input of the cascade.

A random number generating circuit includes M random number generators, where M is an integer greater than or equal to 2, configured to be independent of each other and generate M random number sequences, a delay adjustment circuit configured to output N sets of the M random number sequences including N different relative time differences or N different combinations of a plurality of relative time differences, where N is an integer greater than or equal to 2, by adjusting one or more relative time differences between the M random number sequences, and a logic operation circuit configured to perform an exclusive OR operation between the M random number sequences included in a set, for each of the N sets of the M random number sequences.

A microprocessor that mitigates side channel attacks. The microprocessor includes a data cache memory and a load unit that receive a load operation that specifies a load address. The processor performs speculative execution of instructions and executes instructions out of program order. The load unit detects that the load operation does not have permission to access the load address or that the load address specifies a location for which a valid address translation does not currently exist and provides random load data as a result of the execution of the load operation.

A method, a computer system, and a computer program product for detection of unintended dependencies between hardware design signals from pseudo-random number generator (PRNG) taps is provided. Embodiments of the present invention may include identifying one or more tap points in a design as an execution sequence. Embodiments of the present invention may include sampling the tap points by propagating the tap points in the design with different delays. Embodiments of the present invention may include defining observation points to identify tap collisions based on the tap points. Embodiments of the present invention may include identifying tap collisions. Embodiments of the present invention may include identifying one or more sources of the tap collisions in the design. Embodiments of the present invention may include eliminating the one or more sources of uninteresting tap collisions out of the tap collisions and filtering one or more of the tap collisions.

A pseudo-random number generation circuit device includes a pseudo-random number generation circuit including a logic circuit configured based on rule data that generates a next random number value from a current random number value, a cycle detection circuit that detects, based on a seed, an end of a cycle of random numbers, which are generated by the pseudo-random number generation circuit, and a rule data generation circuit that generates new rule data at a first trigger, at which the cycle detection circuit detects the end of the cycle of random numbers, to output the new rule data to the pseudo-random number generation circuit, wherein the cycle detection circuit stores a random number value, which is generated by a new logic circuit configured based on the new rule data, as the seed.

A pseudo-random number generation circuit device includes a pseudo-random number generation circuit including a logic circuit configured based on rule data that generates a next random number value from a current random number value, a cycle detection circuit that detects, based on a seed, an end of a cycle of random numbers, which are generated by the pseudo-random number generation circuit, and a rule data generation circuit that generates new rule data at a first trigger, at which the cycle detection circuit detects the end of the cycle of random numbers, to output the new rule data to the pseudo-random number generation circuit, wherein the cycle detection circuit stores a random number value, which is generated by a new logic circuit configured based on the new rule data, as the seed.

According to one embodiment, an apparatus is capable of exchanging a frame with an external apparatus in a packet mode of a serial attached small computer system interface (SAS). The external apparatus includes a scrambler. The apparatus includes a descrambler and a controller. The descrambler is configured to descramble frame data scrambled by the scrambler. The controller is configured to, in a case where first frame data is received from the external apparatus, synchronize the descrambler with the scrambler using the first frame data and a first value that is to be scrambled by the scrambler to obtain the first frame data.

Physically unclonable functions response in memory cells is improved by transistor sizing, transistor threshold voltage (V.sub.T) and body bias in the memory cell to improve the reproducibility of the memory cell and multiple Sense Amplifiers (SA) per column to further enhance physically unclonable function entropy. A physically unclonable function exploits a large number of read-sequence-order combinations available in a physically unclonable function memory array to generate an exponentially large challenge-response pair space, without incurring the area and energy costs of hosting and operating an exponentially large memory array.

Methods, systems, and devices for a programmable finite field generator for memory are described. In some cases, a system (e.g., a memory system, a host system) may store coefficient values indicating Galois Field multipliers in an array of configuration registers associated with a finite field generator. To update a set of values stored in a set of registers associated with the finite field generator, the system may perform a set of Galois Field multiplication operations according to Galois Field multipliers indicated by the coefficient values stored in the array of configuration registers. The system may perform at least one Galois Field summation operation on one or more of the multiplied values to generate an updated value. Then, the system may store the updated value in a first register from the set of registers, and shift the set of values along the remaining set of registers.

A true random number generation device and a true random number generation method are provided. The true random number generation device includes a selection signal providing circuit and a linear feedback shift register. The selection signal providing circuit is configured to provide a true random selection signal. The linear feedback shift register includes true random number generators of a plurality of stages. The Nth stage true random number generator is configured to receive a clock signal and a N1th bit true random number. The Nth stage true random number generator generates a plurality of Nth stage output logic values according to the clock signal and the N1th bit true random number, and selects one of the plurality of Nth stage output logic values to be a Nth bit true random number according to the true random selection signal.