A measurement system may measure a fractional time delay of transmission of a signal across a medium, such as a cable. The system may use a first clock to assist in creating and injecting an injected sequence (signal) into the medium. A second, slower clock may be used for sampling the sequence after transmission of the sequence through the medium. This causes a time Vernier scale effect that results in a sampled sequence that has a one-step skip for each instances of the sequence, where the sequence has N elements in the sequence. The location of the skip within the sequence will depend on the magnitude of the delay measured as a fraction of a clock period with a resolution of N. To measure this delay, a modified version of a pseudo-random sequence generator, capable of skipping one step, is used to determine the output.

A device includes parallel connected ring oscillators, a pseudo random number generator (PRNG), and a configuration circuit. The parallel connected ring oscillators include a first and second ring oscillator. The PRNG is configured to generate pseudo random bits at every cycle. The configuration circuit is configured to receive and parse the pseudo random bits to generate and distribute a first configuration value and second configuration value based on the pseudo random bits. The first ring oscillator is configured according to the first configuration value. The second ring oscillator is configured according to the second configuration value.

An apparatus and method for cyclic redundancy check device is provided. The apparatus includes a multiplicity of sub-block CRC parts configured to receive a bit sequence from each sub-block of a transport block that is divided into a multiplicity of sub-blocks and to perform CRC, and a Galois field adding part configured to add second codes, which are output from the multiplicity of sub-block CRC parts, in a Galois field, wherein each sub-block CRC part includes a Galois field multiplying part configured to generate a weight bit sequence by multiplying a first code, which is obtained from CRC calculation of a sub-block weight code that represents a weight allocated to each sub-block, and the bit sequence in the Galois field, and a linear feedback shift register including n-numbered registers and configured to output the second code by adding the weight bit sequence to each register in the Galois field.

High-speed PRBS-N pattern generator, error detector and error counter circuits are provided that have relatively simple circuit configurations, that quickly synchronize and align the input data with the generated pattern, that easily and quickly detect the occurrence of a bit shifting event, and that quickly resynchronize and realign the input data with the generated pattern after a bit shifting event has occurred. The error counter may be implemented with low-speed circuitry even though the pattern generator and error detector operate at the same speed as the high-speed input data signal. This reduces the complexity and power consumption of the error counter.

The present invention discloses a pseudo-random bit sequence (PRBS) generator which outputs the entire datapath, or entire pseudo-random bit sequence, over one single clock cycle. This is accomplished by removing redundancy, or any redundant exclusive-or gates from linear feedback shift registers; using logic to identify the critical path and optimal shift for the critical path; and dividing the datapath into several pipeline stages to increase the clock rate (i.e., transmission speed).

An entropy source and a random number (RN) generator are disclosed. In one aspect, a low-energy entropy source includes a magneto-resistive (MR) element and a sensing circuit. The MR element is applied a static current and has a variable resistance determined based on magnetization of the MR element. The sensing circuit senses the resistance of the MR element and provides random values based on the sensed resistance of the MR element. In another aspect, a RN generator includes an entropy source and a post-processing module. The entropy source includes at least one MR element and provides first random values based on the at least one MR element. The post-processing module receives and processes the first random values (e.g., based on a cryptographic hash function, an error detection code, a stream cipher algorithm, etc.) and provides second random values having improved randomness characteristics.

Disclosed are systems and techniques for parallel deterministic stochastic rounding. In one embodiment, the techniques include obtaining a first set of values of a first bit-length and a second set of values of the first bit-length and generating a third set of values of a second bit-length. Each value of the third set of values is a lower precision value of a corresponding value of the first set of values. The techniques include generating a fourth set of values of the second bit-length, and each value of the fourth set of values is a lower precision value of a corresponding value of the second set of values. Generating the third set of values and the fourth set of values is performed in parallel.

One aspect provides a dual-scale counter circuit that includes a counter logic unit to store a current counter value, a range-determination logic unit to determine an operating range of the dual-scale counter circuit based on the current counter value and a predetermined threshold value, and a counter-increment logic unit. The counter-increment logic unit is to increment the current counter value linearly for an increment event in response to the dual-scale counter circuit operating in a linear range and increment the current counter value probabilistically for the increment event in response to the dual-scale counter circuit operating in a probabilistic range. The dual-scale counter circuit further includes a linear-feedback shift register to generate a random binary bit sequence, based on which the counter-increment logic unit is to determine whether to increase the current counter value for the increment event when the dual-scale counter circuit operates in the probabilistic range.

Electronic devices, circuitry, and methods are provided to efficiently generate a dither signal. An electronic device may include an output device, such as a speaker, to output a media signal, such as an audio signal, based on dithered media data, such as dithered audio data. The electronic device may include dithering circuitry to generate a dither signal, based on a first pseudorandom signal from a first linear feedback shift register and a second pseudorandom signal from a second linear feedback shift register, to add to the media signal to generate the dithered media signal.