A system for providing cross-exception event handling is provided. The system allows a source thread to throw an event (e.g., exception) as part of structured event handling of a programming language that specifies a target thread. When the event is thrown, the source thread starts a handler thread to handle the event in a current context of the target thread. The handler thread is passed an indication of the event and the target thread and sets its context to be consistent with that of handling events in the target thread. The handler thread then handles the event. The source thread may continue its execution in parallel or may terminate its execution as specified in a statement that threw the event. Execution of the target thread may be aborted and its execution continued at an exit statement of an enclosing structured event handling construct—as specified when the event was thrown.

Described are examples for deploying workloads in a cloud-computing environment. In an aspect, based on a desired number of workloads of a process to be executed in a cloud-computing environment and based on one or more failure probabilities, an actual number of workloads of the process to execute in the cloud-computing environment to provide a level of service can be determined and deployed. In another aspect, a standby workload can be executed as a second instance of the process without at least a portion of the separate configuration used by the multiple workloads, and based on detecting termination of one of multiple workloads, the standby workload can be configured to execute based on the separate configuration of the separate instance of the process corresponding to the one of the multiple workloads.

A method for debugging a processor which is executing vertices of a software application is described. Each vertex is assigned to a programming thread of the processor. The processor has debug hardware for raising exceptions in certain break conditions. The method comprises inspecting a vertex identifier, comparing the vertex identifier and raising an instruction exception event for the programming thread if the vertex identifier assigned to the thread matches the vertex break identifier in the debug hardware. Exceptions are raised based on identified vertices, rather than just individual instructions or instruction addresses.

Example implementations relate to method and system for storing and applying updates to a firmware at runtime of a processor-based system. The processor-based system includes a system management (SM) memory, a platform hardware, a main processor, the firmware, and a hotfix-framework. The hotfix-framework includes a hotfix dispatcher module and a service driver module having one or more boot time resources. The firmware and the hotfix-framework are pre-executed in the SM memory. The platform hardware stores a hotfix-firmware including updates to the firmware into a memory of the processor-based system, and generates an interrupt to direct the main processor into an SM mode and get the hotfix-framework notification about the hotfix-firmware. The hotfix dispatcher module loads the hotfix-firmware from the memory into the SM memory, and executes the hotfix-firmware by utilizing the one or more boot time resources to apply the updates to the firmware at runtime of the processor-based system.

Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry 8. In response to a realm switch from a source realm to a target realm at a more privileged exception level, state masking of a subset of architectural state associated with a source realm is performed to make the state inaccessible to a target realm. In response to a flush command following the realm switch, any of the subset of architectural state data not already saved to at least one realm execution context memory region is ensured to be saved.

Apparatus and Method for Fault Handling of an Offload Transaction. For example, one embodiment of a processor comprises: a plurality of cores; an interconnect coupling the plurality of cores; and offload circuitry to transfer work from a first core of the plurality of cores to a second core of the plurality of cores without operating system (OS) intervention, the work comprising a plurality of instructions; the second core comprising first fault management logic to determine an action to take responsive to a fault condition, wherein responsive to detecting a first type of fault condition, the first fault management logic is to cause the first core to be notified of the fault condition, the first core comprising second fault management logic to attempt to resolve the fault condition.

A system, method, apparatus, and computer program product for exception handling between a robotic process automation system and a human operator where the exception is conveyed to the human via a messaging service. The exception is processed by a form algorithm which presents a graphical user interface via a dynamic web form that elicits human input of missing data elements. In cooperation with a validation algorithm, the dynamic web form ensures all missing data elements are provided by the human operator in the desired format. The dynamic web form allows a human to submit the requisite missing data elements, clear entered data elements, and mark the exception for offline processing.

A method for a platform-based scheduling of a job flow is provided, which relates to the technology field of satellites. Specifically, the method includes: acquiring satellite remote sensing data according to transit time of a satellite and triggering a processing flow of the satellite remote sensing data; determining an execution order of the processing flow of the satellite remote sensing data according to a constraint relationship; and allocating processing resources to the processing flow in a hierarchical scheduling manner according to the execution order, and executing the processing flow with the processing resources. Due to a reasonable determination of the execution order of the processing flow of the satellite remote sensing data and a scheduling of the processing resources in the hierarchical scheduling manner, a reasonable allocation of the processing resources is realized. Thus, A timeliness of the processing of the satellite remote sensing data may be improved.

An apparatus has processing circuitry 4 supporting a number of security domains, and within each domain supporting a number of modes including a handler mode for exception processing and a thread mode for background processing. For an exception entry transition from secure thread mode to secure handler mode, a transition disable indicator 42 is set. For at least one type of exception return transition to processing in the secure domain and the thread mode when the transition disable indicator 42 is set, a fault is signaled. This can protect against some security attacks.

The present invention is a novel RTOS/OS architecture that changes the fundamental way that data is organized and context switching is performed. This novel approach consists of a context switching method in which interrupts are never disabled. This RTOS/OS architecture requires specialized hardware. Concretely, an advanced interrupt controller that supports nesting and tail chaining of prioritized interrupts is needed (e.g. the Nested Vectored Interrupt Controller (NVIC) found on many ARM processors) is required. The novel RTOS/OS architecture does not keep the list of tasks ready to run in sorted order, allowing for O(1) insertion time and utilizes a barrier variable to allow for safe O(n) insertion of tasks into the priority sorted list of blocked tasks without disabling interrupts. The advanced interrupt controller allows for any new interrupts to preempt the software exception handler thereby ensuring no data loss. This novel RTOS/OS architecture eliminates the diabolical deficiency existent in current architectures which creates a superficial dependency between the number of tasks in the system and the maximum bandwidth that can be sustained at some peripheral. That is, this architecture ensures that the maximum bandwidth never decreases as more tasks are added to the system.