An apparatus comprises: processing circuitry to perform data processing in one of a plurality of security domains including at least a secure domain and a less secure domain, and memory access checking circuitry to check whether a memory access is allowed depending on security attribute data indicating which domain is associated with a target address. In response to a given change of program flow from processing in the less secure domain to a target instruction having an address associated with the secure domain: a fault is triggered when the target instruction is an instruction other than a gateway instruction indicating a valid entry point to the secure domain. When the target instruction is said gateway instruction, a stack pointer verifying action is triggered to verify whether it is safe to use a selected stack pointer stored in a selected stack pointer register.

A Data Storage Device (DSD) includes a memory for storing data, and a controller configured to execute firmware or code to perform a task. While performing the task, the controller is further configured to assign unique identifiers to respective firmware or code portions that are executed to perform the task, and create a list or data structure including the unique identifier assigned to the firmware or code portion that created the task. A unique identifier is added to the list or data structure for each firmware or code portion executed for the task. The list or data structure indicates the order in which the firmware or code portions are executed.

Interrupt code conversion for efficient computer program recovery. In response to an error being detected while processing instructions of a computer program running on a computer system, the OS receives a first program interrupt code (PIC) and interrupts the computer program. Control of the computer program is passed to a program interrupt handler and the program interrupt handler inspects the first PIC issued as a result of detecting the error. The first PIC is converted to a second PIC wherein the second PIC is associated with another error predicted when subsequent running of the computer program occurs. The second PIC is presented to a recovery routine associated with the computer program and, in response to the detected error, running of the computer program is customized based on the second PIC rather than the first PIC.

An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

Providing exception stack management using stack panic fault exceptions in processor-based devices is disclosed. In this regard, a processor device defines a “stack panic fault exception” that may be raised upon execution of an exception handler store operation attempting to write state data into an exception stack, and provides a dedicated plurality of stack panic fault exception state registers in which stack panic fault exception state data may be saved. Upon detecting a first exception, the processor device transfers program control to an exception handler for the first exception. If a second exception occurs upon execution of a store operation in the exception handler, the processor device determines that the second exception should be handled as a stack panic fault exception, saves the stack panic fault exception state data in the stack panic fault exception state registers, and transfers program control to a stack panic fault exception handler.

An interrupt system for RISC-V architecture includes an original register in a CLIC, a pushmcause register, a pushmepc register, an interrupt response register, and an mtvt2 register; the pushmcause register is used to store a value in an mcause on a stack by means of an instruction; the pushmepc register is used to store a value in an mepc on a stack by means of an instruction; the interrupt response register is used to respond to a non-vectored interrupt request issued by a CLIC by means of an instruction, obtain an interrupt subroutine entry address, and modify a global interrupt enable; and the mtvt2 register is used to store a base address of an non-vectored interrupt in a CLIC mode.

Example method includes: allocating, by a main processor of a wireless access point (WAP) comprising at least the main processor and a plurality of co-processors wherein the main processor and the plurality of co-processors both have access to a random-access memory (RAM) co-located within the WAP, a dedicated non-overlapping segment of the RAM to each of the plurality of the co-processors; receiving, by the main processor of the WAP, a notification from one of the plurality of co-processors indicating that an exception previously defined by the one of the plurality of co-processors has occurred; determining, by the main processor of the WAP, the dedicated non-overlapping segment of the RAM allocated to the one of the plurality of co-processors; and saving, by the main processor of the WAP, the dedicated non-overlapping segment of the RAM allocated to the one of the plurality of co-processors to a fast access memory.

A method of managing a stack includes detecting, by a stack manager of a processor, that a size of a frame to be allocated exceeds available space of a first stack. The first stack is used by a particular task executing at the processor. The method also includes designating a second stack for use by the particular task. The method further includes copying metadata associated with the first stack to the second stack. The metadata enables the stack manager to transition from the second stack to the first stack upon detection that the second stack is no longer in use by the particular task. The method also includes allocating the frame in the second stack.

A class unloading method comprises: loading, by an electronic device, n classes after an application is started, where n is a positive integer; generating a reference mapping table, where the reference mapping table includes a reference relationship between the n classes and m class objects corresponding to the n classes and a dependency relationship between the m class objects corresponding to the n classes, the dependency relationship is used to represent an interdependency mapping relationship between different class objects, and m is a positive integer greater than or equal to n; and unloading a first class of the n classes based on the reference mapping table in an operation process of the application.

The present disclosure provides an exception stack handling method, system, electronic device and storage medium and relates to the field of mobile Internet. The method may include: at the level of any executor in a distributed stream-type processing system including at least two executors, performing the following processing of: obtaining at least one exception stack from a message middleware when the executor in an idle state each time, collected exception stacks generated by users being stored in the message middleware; as for any exception stack, obtaining an anti-obfuscation map file corresponding to the exception stack, and performing anti-obfuscation processing for the exception stack by using the anti-obfuscation map file. The solution of the present disclosure may be applied to improve the processing speed.