Disclosed is a task allocation method, apparatus, electronic device, and computer-readable storage medium. The task allocation method includes: in response to receiving a synchronization signal, executing, by the master processing core, a task update instruction to obtain a to-be-executed task segment; receiving, by a processing core for executing the task, the to-be-executed task segment, wherein the processing core for executing the task includes the master processing core and/or the slave processing core; executing, by the processing core for executing the task, the to-be-executed task segment; and in response to completion of execution of the to-be-executed task segment, sending, by the processing core for executing the task, a synchronization request signal, wherein the synchronization request signal is configured to trigger generation of the synchronization signal.

A system, method and computer-readable media for managing a compute environment are disclosed. The method includes importing identity information from an identity manager into a module performs workload management and scheduling for a compute environment and, unless a conflict exists, modifying the behavior of the workload management and scheduling module to incorporate the imported identity information such that access to and use of the compute environment occurs according to the imported identity information. The compute environment may be a cluster or a grid wherein multiple compute environments communicate with multiple identity managers.

An apparatus and method are described for efficiently processing and reassigning interrupts. For example, one embodiment of an apparatus comprises: a plurality of cores; and an interrupt controller to group interrupts into a plurality of interrupt domains, each interrupt domain to have a set of one or more interrupts assigned thereto and to map the interrupts in the set to one or more of the plurality of cores.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing computational graphs on distributed computing devices. One of the methods includes receiving a request to execute a processing pipeline (i) first operations that transform raw inputs into pre-processed inputs and (ii) second operations that operate on the pre-processed inputs; and in response: assigning the first operations to two or more of a plurality of computing devices, assigning the second operations to one or more hardware accelerators of a plurality of hardware accelerators, wherein each hardware accelerator is interconnected with the plurality of computing devices, and configured to (i) receive inputs from respective queues of the two or more computing devices assigned the first operations and (ii) perform the second operations on the received pre-processed inputs, and executing, in parallel, the processing pipeline on the two or more computing devices and the one or more hardware accelerators.

A multi-core processor system and a method for assigning tasks are provided. The multi-core processor system includes a plurality of processor cores, configured to perform a plurality of tasks, and each of the tasks is in a respective one of a plurality of scheduling classes. The multi-core processor system further includes a task scheduler, configured to obtain first task assignment information about tasks in a first scheduling class assigned to the processor cores, obtain second task assignment information about tasks in one or more other scheduling classes assigned to the processor cores, and refer to the first task assignment information and the second task assignment information to assign a runnable task in the first scheduling class to one of the processor cores.

Embodiments are generally directed apparatuses, methods, techniques and so forth to select two or more processing units of the plurality of processing units to process a workload, and configure a circuit switch to link the two or more processing units to process the workload, the two or more processing units each linked to each other via paths of communication and the circuit switch.

An architecture for a load-balanced groups of multi-stage manycore processors shared dynamically among a set of software applications, with capabilities for destination task defined intra-application prioritization of inter-task communications (ITC), for architecture-based ITC performance isolation between the applications, as well as for prioritizing application task instances for execution on cores of manycore processors based at least in part on which of the task instances have available for them the input data, such as ITC data, that they need for executing.

A method is provided for configuring an SIL simulation of a control unit running on a computer, software modules for the control unit, which have a plurality of tasks, being installed on the computer for the SIL simulation of the control unit, the tasks being processed in a predetermined clock cycle having a periodic period between the individual clock time points, and the computer including a plurality of processor cores, on which a plurality of virtual machines run, which each process predetermined tasks. A possibility is thus provided for minimizing the computing time of an SIL test.

An exclusive control processing that is complex is eliminated on tasks executed in processors. A semiconductor device includes: a memory that stores task management information and running group management information; a first PE and a second PE; and a first shared resource and a second shared resource, and the first PE or the second PE is configured to refer to the running group management information and specify a group of tasks executable in the first PE or the second PE as an executable group, and to refer to the task management information and determine a task associated with group identification information of the specified executable group as a task to be executed next in the first PE or the second PE.

[Problem] To reduce processing load on the CPU driving an OS.

[Solution] This device is provided with a multicore microprocessor unit (21) capable of inter-processor communication, a storage means (22) for storing a file describing device configuration information, and a device interface (23). Threads of the microprocessor unit are separated: a first processor core drives the OS, and meanwhile, a second processor core drives the device driver for controlling the device interface. While sharing the device configuration information by inter-processor communication, a notification driver interface for notifying the operating system kernel of configuration information on the basis of the device configuration information is loaded and the second processor core controls the device connected to the device interface by reading a scenario sequence file into the notification driver.