G06F2209/507

MEMORY FRAGMENTS FOR SUPPORTING CODE BLOCK EXECUTION BY USING VIRTUAL CORES INSTANTIATED BY PARTITIONABLE ENGINES
20180157491 · 2018-06-07 ·

A global front end scheduler to schedule instruction sequences to a plurality of virtual cores implemented via a plurality of partitionable engines. The global front end scheduler includes a thread allocation array to store a set of allocation thread pointers to point to a set of buckets in a bucket buffer in which execution blocks for respective threads are placed, a bucket buffer to provide a matrix of buckets, the bucket buffer including storage for the execution blocks, and a bucket retirement array to store a set of retirement thread pointers that track a next execution block to retire for a thread.

MANAGEMENT OF RESOURCES WITHIN A COMPUTING ENVIRONMENT

Resources in a computing environment are managed, for example, by a hardware controller controlling dispatching of resources from one or more pools of resources to be used in execution of threads. The controlling includes conditionally dispatching resources from the pool(s) to one or more low-priority threads of the computing environment based on current usage of resources in the pool(s) relative to an associated resource usage threshold. The management further includes monitoring resource dispatching from the pool(s) to one or more high-priority threads of the computing environment, and based on the monitoring, dynamically adjusting the resource usage threshold used in the conditionally dispatching of resources from the pool(s) to the low-priority thread(s).

Resource sharing using process delay
09940168 · 2018-04-10 · ·

Methods and systems that reduce the number of instance of a shared resource needed for a processor to perform an operation and/or execute a process without impacting function are provided. a method of processing in a processor is provided. Aspects include determining that an operation to be performed by the processor will require the use of a shared resource. A command can be issued to cause a second operation to not use the shared resources N cycles later. The shared resource can then be used for a first aspect of the operation at cycle X and then used for a second aspect of the operation at cycle X+N. The second operation may be rescheduled according to embodiments.

MULTI-THREAD PROCESSOR AND CONTROLLING METHOD THEREOF

A multi-thread processor and a method of controlling a multi-thread processor are provided. The multi-thread processor includes at least one functional unit; a mode register; and a controller configured to control the mode register to store thread mode information corresponding to a task to be processed among a plurality of thread modes, wherein the plurality of thread modes are divided based on a size and a number of at least one thread that is concurrently processed in one of the at least one functional unit, allocate at least one thread included in the task to the at least one functional unit based on the thread mode information stored in the mode register and control the at least one functional unit to process the at least one thread.

Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
09921845 · 2018-03-20 · ·

A system for executing instructions using a plurality of memory fragments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality memory fragments are coupled to the partitionable engines for providing data storage.

APPARATUS, SYSTEM AND METHOD FOR PROXY COUPLING MANAGEMENT
20180018199 · 2018-01-18 ·

An apparatus, system, and method are disclosed for proxy coupling management. A proxy template module transparently offloads a task from a native data processing system to an equivalent task on a remote data processing system. A proxy generation module fills in the proxy template with information, such as specification of an offload task that is a remote equivalent of the native task, to generate a proxy of the native task. An offload agent module receives a request from the proxy to perform the offload task on the remote data processing system.

Management of resources within a computing environment

Resources in a computing environment are managed, for example, by a hardware controller controlling dispatching of resources from one or more pools of resources to be used in execution of threads. The controlling includes conditionally dispatching resources from the pool(s) to one or more low-priority threads of the computing environment based on current usage of resources in the pool(s) relative to an associated resource usage threshold. The management further includes monitoring resource dispatching from the pool(s) to one or more high-priority threads of the computing environment, and based on the monitoring, dynamically adjusting the resource usage threshold used in the conditionally dispatching of resources from the pool(s) to the low-priority thread(s).

Selecting processor micro-threading mode

An approach is provided to dynamically select a micro-threading (MT) mode of each core of a processor based on a load on each of the respective cores while the processor is running a hypervisor. The approach sets a core's micro-threading mode to a whole-core mode (MT1) in response to identifying that the load on the selected core is at a light load level, sets the core's micro-threading mode to a two-way micro-threading mode (MT2) in response to identifying that the load on the selected core has increased above the light load level, and sets the selected core's micro-threading mode to a four-way micro-threading mode (MT4) in response to identifying that the load on the selected core is at a high load level.

Selecting processor micro-threading mode

An approach is provided to dynamically select a micro-threading (MT) mode of each core of a processor based on a load on each of the respective cores while the processor is running a hypervisor. The approach sets a core's micro-threading mode to a whole-core mode (MT1) in response to identifying that the load on the selected core is at a light load level, sets the core's micro-threading mode to a two-way micro-threading mode (MT2) in response to identifying that the load on the selected core has increased above the light load level, and sets the selected core's micro-threading mode to a four-way micro-threading mode (MT4) in response to identifying that the load on the selected core is at a high load level.

SCHEDULING EXECUTION OF INSTRUCTIONS ON A PROCESSOR HAVING MULTIPLE HARDWARE THREADS WITH DIFFERENT EXECUTION RESOURCES
20170192779 · 2017-07-06 ·

A method and apparatus are provided for executing instructions of a multi-threaded processor having multiple hardware threads with differing hardware resources comprising the steps of receiving a plurality of streams of instructions and determining which hardware threads are able to receive instructions for execution, determining whether a thread determined to be available for executing an instructions has the hardware resources available required by that instructions and executing the instruction in dependence on the result of the determination.