Patent classifications
G06F2209/509
Device, system and method for processing data
A method, apparatus and computer program product, the method comprising: receiving by a device present at a mobile environment, data relating to a computerized task; obtaining information related to a future state of the device or the mobile environment or another device within the mobile environment; determining indications for resource availability associated with the future state; determining a scheme for performing at least part of the computerized task offsite, in accordance with the resource availability; and transmitting data over a communication channel to a remote computing platform for performing the at least part of the computerized task offsite, in accordance with the scheme.
INFORMATION REPORTING METHOD, APPARATUS AND DEVICE, AND STORAGE MEDIUM
Described are an information reporting method, apparatus and device, and a storage medium. The method includes: a terminal sends AI/ML capability information to a network device, the AI/ML capability information indicating resource information of a terminal for processing an AI/ML service; the network device, according to the AI/ML capability information reported by the terminal, can flexibly switch an AI/ML model run by the terminal, distribute an appropriate AI/ML model for the terminal, and adjust AI/ML training parameters and the like. Therefore, while it is ensured that an AI/ML task can be completed, AI/ML resources such as the processing capability, storage capability, and battery of the terminal can be utilized more efficiently, so that the reliability, timeliness and efficiency of AI/ML operations based on a terminal are ensured.
FPGA-based dynamic graph processing method
The present disclosure relates to an FPGA-based dynamic graph processing method, comprising: where graph mirrors of a dynamic graph that have successive timestamps define an increment therebetween, a pre-processing module dividing the graph mirror having the latter timestamp into at least one path unit in a manner that incremental computing for any vertex only depends on a preorder vertex of that vertex; an FPGA processing module storing at least two said path units into an on-chip memory directly linked to threads in a manner that every thread unit is able to process the path unit independently; the thread unit determining an increment value between the successive timestamps of the preorder vertex while updating a state value of the preorder vertex, and transferring the increment value to a succeeding vertex adjacent to the preorder vertex in a transfer direction determined by the path unit, so as to update the state value of the succeeding vertex.
Scheduling services on a platform including configurable resources
Technology related to scheduling services on a platform including configurable computing resources is disclosed. In one example, a method includes scheduling a service to execute on a first computing node based on an availability of general-purpose computing resources at the first computing node. The first computing node can be selected from a plurality of computing nodes. Network traffic transiting the first computing node can be analyzed during the execution of the service to determine a hardware accelerator of a second computing node is capable of assisting the execution of the service. The service can be scheduled to execute on the second computing node and the hardware accelerator of the second computing node can be used to assist with the execution of the service.
SERVER AND ACCELERATOR FOR NEURAL NETWORK COMPUTATIONS
Disclosed are an acceleration unit for executing a neural network model and a server. The acceleration unit includes: a plurality of cluster groups, where each of the cluster groups includes a plurality of processing clusters; an on-chip memory, including a plurality of storage units, where each storage unit corresponds to each of the cluster groups, and is configured to store an instruction sequence and operation data of the corresponding cluster group; a command processor, configured to decompose an operation associated with a specified neural network model into a plurality of sub-operations, convert the plurality of sub-operations into a plurality of instruction sequences, specify operation data of each of the instruction sequences; and a plurality of distribution units, where each distribution unit reads the instruction sequence and operation data of the instruction sequence from the corresponding storage unit into the corresponding cluster group.
IMAGE PROCESSING METHOD AND APPARATUS, COMPUTER DEVICE, AND STORAGE MEDIUM
An image processing method includes: obtaining a target compression texture resource of a target image, the target compression texture resource including a plurality of compression texture blocks; allocating a plurality of target work groups for decoding to the plurality of compression texture blocks in a graphic card shader, and distributing each compression texture block to a corresponding target work group; and decoding in parallel, by the target work groups in the graphic card shader, the compression texture blocks according to the compression texture format, to obtain target texture data of the target image, the target texture data comprising decoded data corresponding to the compression texture blocks.
COMPUTATION OFFLOADING METHOD AND COMMUNICATION APPARATUS
A computation offloading method and an apparatus. In network edge computation offloading, an edge node receives states of computational tasks sent by one or more served terminal devices and determines allocation of computing resources based on received states of one or more computational tasks. Then, the edge node broadcasts the allocation of the computing resources to the served terminal devices, and the terminal devices each determine, based on the resource allocation, whether to offload the computational task to the edge node for computing. Therefore, the edge node and the terminal device each can have a wider capability of sensing an environment in actual decision-making, thereby effectively improving decision-making benefits of the edge node and the terminal device.
SUPPORTING PROCESSING-IN-MEMORY EXECUTION IN A MULTIPROCESSING ENVIRONMENT
A processor for supporting PIM (Processing-in-Memory) execution in a multiprocessing environment includes logic configured to: receive a request to initiate an offload of a number of PIM instructions to a PIM device. The request is issued by a first thread of a processor. The logic is also configured to reserve, based on information in the request, resources of the PIM device for execution of the plurality of instructions.
System and method for the remote execution of one or more arbitrarily defined workflows
A system for the remote execution of one or more arbitrarily defined workflows comprises a workflow engine operative to perform one or more functions defined in a given workflow on customer computing infrastructure and a workflow administrator with access to a workflow database that maintains metadata defining the state of the given workflow, the workflow administrator remote from the workflow engine and not running on the customer computing infrastructure. A workflow administrator agent polls the workflow administrator to identify when the given workflow is scheduled for execution and, when scheduled, issues a command to the workflow engine to retrieve the given workflow from a workflow registry and perform the one or more functions defined in the given workflow on the customer computing infrastructure. The workflow administrator agent transmits state information regarding execution of the given workflow to the workflow administrator for storage in the workflow database.
ARTIFICIAL NEURAL NETWORK AND COMPUTATIONAL ACCELERATOR STRUCTURE CO-EXPLORATION APPARATUS AND METHOD
An artificial neural network and computational accelerator structure co-exploration apparatus, includes: a neural architecture search (NAS) module configured to determine neural network architecture, and a differentiable accelerator and network co-exploration (DANCE) evaluation module configured to determine accelerator architecture according to the determined neural network architecture and predict hardware metrics for the determined accelerator architecture.