A method and apparatus for simulating target program code on a host data processing apparatus, the simulation mapping load-exclusive instructions in the target program code to load instructions, and mapping store-exclusive instructions in the target program code to compare-and-swap instructions.

Aspects for operating a computer system include a colored lock synchronization object allowing flow specific policy of lock canceling. An extended lock object Application Programming Interface (API) including a color attribute is utilized. A color attribute is passed to the extended lock API, whereby the color attribute reflects a type of flow or thread that called a colored lock object. Selective termination of requests waiting on a colored lock object can be utilized to prevent a potential deadlock condition.

A system for sharing data between two processes implements a memory arranged as a two dimensional ping/pong buffer where a writing operation alternately swaps buffers in one dimension and a reading operation swaps buffers in the other dimension. Accordingly, writing is into one or the other of a reading buffer set not currently being read with each write alternating between the write buffers. Data is retrieved from the buffer that is not currently being written. The buffer switching is coordinated by using commonly accessed variables between the reader and the writer and implements a system that is lock-free.

A method and a system for implementing a lock-free shared memory accessible by a plurality of readers and a single writer are provided herein. The method including: maintaining a memory accessible by the readers and the writer, wherein the memory is a hash table having at least one linked list of buckets, each bucket in the linked list having: a bucket ID, a pointer to an object, and a pointer to another bucket; calculating a pointer to one bucket of the linked list of buckets based on a hash function in response to a read request by any of the readers; and traversing the linked list of buckets, to read a series of objects corresponding with the traversed buckets, while checking that the writer has not: added, amended, or deleted objects pointed to by any of said traversed buckets, wherein said checking is carried out in a single atomic action.

In an embodiment, a processor comprises an atomic predictor circuit to predict whether or not an atomic operation will complete successfully. The prediction may be used when a subsequent load operation to the same memory location as the atomic operation is executed, to determine whether or not to forward store data from the atomic operation to the subsequent load operation. If the prediction is successful, the store data may be forwarded. If the prediction is unsuccessful, the store data may not be forwarded. In cases where an atomic operation has been failing (not successfully performing the store operation), the prediction may prevent the forwarding of the store data and thus may prevent a subsequent flush of the load.

A pair of compute nodes, each having a separate PCIe root complex, are interconnected by a PCIe Non-Transparent Bridge (NTB). An instance of a NTB monitoring process is started for each root complex, and the CPU affinity of the NTB monitoring processes are set to cause each NTB monitoring process to be executed on CPU resources of each respective CPU root complex. The NTB monitoring process on a given root complex is allowed to sleep until a triggering event occurs that causes the NTB monitoring process to wake and determine the state of the NTB. One such triggering event is a failure of an atomicity algorithm on the compute node to obtain a lock on peer memory in connection with implementing an atomic read operation on the peer memory over the NTB.

In example implementations, a method include receiving a request for a lock in a Mellor-Crummey Scott (MCS) lock protocol from a guest user that is context free (e.g., a process that does not bring a queue node). The lock determines that it contains a null value. The lock is granted to the guest user. A pi value is received from the guest user to store in the lock. The pi value notifies subsequent users that the guest user has the lock.

A method and system for implementing a reader-writer lock having a write lock requested by a thread is disclosed. The reader-writer lock is structured to have counters and a flag. The counters use an atomic process to count read locks held or outstanding read lock requests. The flag identifies a counter and is configured to distinguish between counters. A read lock is prepared, acquired, and released. The atomic process is used and the flag or flagged counter is polled. A write lock is prepared, acquired, and released.

A computer system includes a hardware synchronization component (HSC). Multiple concurrent threads of execution issue instructions to update the state of the HSC. Multiple threads may update the state in the same clock cycle and a thread does not need to receive control of the HSC prior to updating its states. Instructions referencing the state received during the same clock cycle are aggregated and the state is updated according to the number of the instructions. The state is evaluated with respect to a threshold condition. If it is met, then the HSC outputs an event to a processor. The processor then identifies a thread impacted by the event and takes a predetermined action based on the event (e.g. blocking, branching, unblocking of the thread).

Instructions and logic provide user-level thread synchronization with MONITOR and MWAIT instructions. One or more model specific registers (MSRs) in a processor may be configured in a first execution state to specify support of a user-level thread synchronization architecture. Embodiments include multiple hardware threads or processing cores, corresponding monitored address state storage to store a last monitored address for each of a plurality of execution threads that issues a MONITOR request, cache memory to record MONITOR requests and associated states for addresses of memory storage locations, and responsive to receipt of an MWAIT request for the address, to record an associated wait-to-trigger state of monitored addresses for execution cores associated with an MWAIT request; wherein the execution core is to transition a requesting thread to an optimized sleep state responsive to the receipt of said MWAIT request when said one or more MSRs are configured in the first execution state.