Patent classifications
G06F2209/543
Key input processing in virtualized computing environment
An example method is provided to process an input in a virtualized computing environment. The virtualized computing environment may include a physical machine running a host operating system and a virtualization software with one or more virtual machines. The example method may include detecting activation of at least one key input that causes a first message to be generated, the first message associated with the key input, comparing the first message with a set of stored messages, wherein any of the set of stored messages can be properly executed by targets in both the host operating system and the virtual machine but with different responses, and determining, based on the comparing, whether the first message is intended for a target in the host operating system or in the virtual machine.
DECOUPLING BACKGROUND WORK AND FOREGROUND WORK
Systems, methods, and apparatus for separately loading and managing foreground work and background work of an application. In some embodiments, a method is provided for use by an operating system executing on at least one computer. The operating system may identify at least one foreground component and at least one background component of an application, and may load the at least one foreground component for execution separately from the at least one background component. For example, the operating system may execute the at least one foreground component without executing the at least one background component. In some further embodiments, the operating system may use a specification associated with the application to identify at least one piece of computer executable code implementing the at least one background component.
MEMORY-BASED CROSS-DOMAIN I/O FRAMEWORK
A cross-domain device includes a memory with a shared memory region. The device further includes a first interface to couple to a first device over a first interconnect, where the first device implements a first domain, and includes a second interface to couple to a second device over a second interconnect, where the second device implements a second domain, and the first domain is independent of the second domain. The cross-domain device is to create a buffer in the shared memory region to allow writes by a first software module in the first domain and reads by a second software module in the second domain, and use the buffer to implement a memory-based communication link between the first software module and the second software module.
Window grouping
A framework is provided for obtaining window information. The window information can be applied to different assignment models to assign windows to different groups. A group may correspond to a task being performed by a user. The window information can be semantic or temporal information captured as window events and properties of windows whose events are captured. Temporal information can be information about switches between windows. Semantic information can be window titles. Temporal information, semantic information, or both, can be used to assign windows to groups.
COMMAND PROCESSING DEVICE AND DISPLAY DRIVING INTEGRATED CIRCUIT INCLUDING THE SAME
A command processing device includes an asynchronous first-in first-out (FIFO) unit, a mode configuration unit and a post processing unit. The asynchronous FIFO unit receives a plurality of commands from an external device, and stores the plurality of commands. The mode configuration unit sets a command processing scheme for each of the plurality of commands to one of a first processing scheme or a second processing scheme different from the first processing scheme and stores the command processing scheme for each of the plurality of commands. The post processing unit determines the command processing scheme for each of the plurality of commands based on the mode configuration unit, and generates a plurality of control signals by processing the plurality of commands based on an input sequence of the plurality of commands and the determined command processing scheme.
SMOOTHING PERIODIC DATA CHANNEL ACCESS
In one aspect, a system comprises: a memory configured to store a plurality of data units; a plurality of data sources, where each data source is configured to provide a respective data unit; and a processor configured to: determine a plurality of periods where each period is associated with a respective event and each event is associated with a different respective data source, determine a plurality of adjusted periods, where each period is associated with a respective adjusted period, determine a respective order for each adjusted period, determine a number of adjusted periods associated with each order, determine a number of time slots for a lowest order of adjusted periods based on the number of adjusted periods within each of the orders, and determine a start time for each event based on the order of the event and the number of time slots for the lowest order of adjusted periods.
SYSTEM AND METHOD FOR MANAGING NAMESPACE OF OFFLOADING CARD AND PROCESSING INPUT/OUTPUT REQUEST
A system and a method for managing a namespace of an offloading card and processing an input/output request. The system for managing the namespace of the offloading card (300) includes a host (301) and an offloading card (302) connected to the host (301), where the host (301) has multiple applications issuing an input/output request running thereon, and the host (301) sends a namespace creation request to the offloading card (302), the offloading card (302) creates corresponding multiple namespaces for the multiple applications according to the namespace creation request, the offloading card (302) allocates multiple hardware queues corresponding to the created multiple namespaces according to the namespace creation request and binds the allocated multiple hardware queues respectively to the corresponding namespaces; multiple namespaces can be created, and dedicated hardware queues can be dynamically allocated for respective namespaces, so that namespace resources in hardware level is achieved.
COMPUTATION ARCHITECTURE CAPABLE OF EXECUTING NESTED FINE-GRAINED PARALLEL THREADS
An accelerator apparatus cooperates with at least one processing core and a memory. The accelerator apparatus includes: a plurality of thread execution units (TEU) configured to execute a plurality of threads in parallel, and a thread buffer interconnected with the thread execution units. Based on an instruction indicating a thread to be executed, the thread buffer retrieves, from the memory, at least some data to be used by the thread. Based on a TEU among the plurality of TEUs being available and the at least some data to be used by the thread being retrieved, the thread buffer provides the thread and the at least some data to the available TEU. The thread buffer is separate from the memory, and the plurality of TEUs is separate from the at least one processing core.
NOTEBOOK COMPUTER AND OPERATION METHOD
A notebook computer and an operation method thereof are provided. The notebook computer includes a platform controller hub (PCH), an embedded controller (EC), a data wiring, a clock signal wiring and an interrupt signal wiring. The platform controller hub includes a first internal integrated circuit (I2C) controller and a general-purpose input/output (GPIO) controller. The embedded controller includes a second internal integrated circuit (I2C) controller. The data wiring is connected to the first I2C controller and the second I2C controller. The clock signal wiring is connected to the first I2C controller and the second I2C controller. The interrupt signal wiring is connected to the GPIO controller and the second I2C controller.
LOCAL LAUNCH IN WORKGROUP PROCESSORS
Workgroup processors associated with a shader program interface are provided with local launchers capable of launching shader threads partially or completely independently from the shader program interface. The local launchers maintain local queues separately from the shader program interface. The local launchers allocate resources for shader thread execution at an associated workgroup processor either directly or through a request to the shader program interface. In some implementations, the shader program interface leases resources to the local launcher in response to a request for resources and terminates the lease when the local launcher notifies the shader program interface that execution of the shader thread is complete.