Aspects of a storage device including a memory and a controller are provided. The memory includes a plurality of non-volatile memory packages coupled to the switch, in which each non-volatile memory package includes a plurality of non-volatile memory dies. The controller can select a non-volatile memory package with the switch. The controller can establish a data channel connection between the selected non-volatile memory package and the controller via the switch. In some aspects, the selected non-volatile memory package is transitioned into an active mode and one or more non-selected non-volatile memory packages are each transitioned into a standby mode. The controller also can perform one or more storage device operations with one or more non-volatile memory dies of the plurality of non-volatile memory dies within the selected non-volatile memory package. Thus, the controller may facilitate a switch based ball grid array extension, thereby improving memory capacity of the storage device.

An integrated circuit that includes a set of one or more logic layers that are, when the integrated circuit is stacked in an assembly with the set of stacked memory devices, electrically coupled to a set of stacked memory devices. The set of one or more logic layers include a coupled chain of processing elements. The processing elements in the coupled chain may independently compute partial results as functions of data received, store partial results, and pass partial results directly to a next processing element in the coupled chain of processing elements. The processing elements in the chains may include interfaces that allow direct access to memory banks on one or more DRAMs in the stack. These interfaces may access DRAM memory banks via TSVs that are not used for global I/O. These interfaces allow the processing elements to have more direct access to the data in the DRAM.

A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.

A data merge method for a rewritable non-volatile memory module including a plurality of physical units is provided. The method includes: selecting at least one first physical unit and at least one second physical unit from the physical units; reading first mapping information from the rewritable non-volatile memory module, and the first mapping information includes mapping information of the first physical unit and mapping information of the second physical unit; copying valid data collected from the first physical unit and valid data collected from the second physical unit to at least one third physical unit of the physical units according to the first mapping information; and when a data volume of valid data copied from the second physical unit to the third physical unit reaches a data volume threshold, stopping collecting valid data from the second physical unit, and continuing collecting valid data from the first physical unit.

A method for performing access management of a memory device with aid of a Universal Asynchronous Receiver-Transmitter (UART) connection and associated apparatus are provided. The method may include: utilizing a UART of a memory controller within the memory device to receive a set of intermediate commands corresponding to a set of operating commands through the UART connection between the memory device and a host device, wherein before sending the set of intermediate commands to the controller through the UART connection, the host device converts the set of operating commands into the set of intermediate commands; converting the set of intermediate commands into the set of operating commands according to a command mapping table; and accessing a non-volatile (NV) memory within the memory device with the set of operating commands for the host device, and sending a response to the host device through the UART connection.

Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to PCIe Address Translation Service (ATS) to allow devices to have a DevTLB that caches address translation (per page) information in conjunction with a Device ProcessInfoCache (DevPIC) that will store process specific information. Other embodiments may be described and/or claimed.

A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.

A technique deploys a virtualization layer underneath an operating system executing on a node of a network environment to enable the virtualization layer to control the operating system is described. One or more executables (binaries) for the virtualization layer may be included in a kernel module loaded in memory of the node with a first privilege level (e.g., highest privilege level) needed to control the guest operating system. The kernel module may be configured to suspend the guest operating system and one or more hardware resources to a quiescent state. Furthermore, the kernel module is configured to (i) capture and save states of the hardware resource(s) and (ii) bootstrap the virtualization layer to create a virtual machine with an initial state that corresponds to a state of the system prior to deployment of the virtualization layer.

A method comprises identifying a first page in a computer readable memory communicatively coupled to the apparatus that has been marked as being stored in memory as plaintext even if accessed using cryptographic addresses, the first page in the computer readable memory comprising at least one encrypted data object, and set a page table entry bit for the first page to a first value which indicates that at least one memory allocation in the first page has been marked as being stored in memory as plaintext even if accessed using cryptographic addresses.

A storage access request to access a solid state drive (SSD) is received. A storage access timer is set with a time duration, where the time duration is based on a desired performance of the SSD. A non-volatile memory command associated with the storage access request is sent to non-volatile memory. The storage access timer is started. A determination is made whether the non-volatile memory completed execution of the non-volatile memory command after the storage access timer indicates that the time duration elapsed. An indication that the storage access request is complete is sent to a host if the non-volatile memory completed execution of the non-volatile memory command. Alternatively, the storage access timer is reset with the time duration if the non-volatile memory has not completed execution of the non-volatile memory command.