Packet-processing circuitry including one or more flow caches whose contents are managed using a cache-entry replacement policy that is implemented based on one or more updatable counters maintained for each of the cache entries. In an example embodiment, the implemented policy enables the flow cache to effectively catch and keep elephant flows by giving to the caught elephant flows appropriate preference in terms of the cache dwell time, which can beneficially improve the overall cache-hit ratio and/or packet-processing throughput. Some embodiments can be used to implement an Open Virtual Switch (OVS). Some embodiments are advantageously capable of implementing the cache-entry replacement policy with very limited additional memory allocation.

An electronic system includes; a host providing a command and source data having a source data structure, a computing resource device operating in relation to destination data having a destination data structure different from the source data structure, and a storage device. The storage device receives the command from the host and includes a storage medium storing the source data, and a data reorganizing unit converting the source data into reorganized source data, wherein the storage device outputs the reorganized source data to the computing resource device as destination data.

Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing pins of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided through the pins of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.

A computing device, including a processor; a memory, wherein the memory is accessible for memory operations via a range of logical memory addresses; a peripheral interface including a first control register; and a peripheral address remapping module configured to determine that the peripheral interface is unused for interfacing with a peripheral; determine a first memory address for accessing the first control register; determine a first logical memory address, the first logical memory address outside of the range of logical memory addresses for accessing the memory; and map the first logical memory address to the first memory address, wherein the first control register is accessible for memory operations using the first logical memory address.

A quantum cache includes a quantum store having an input that receives a quantum state having fundamental quantum properties comprising coherence and is configured to store the quantum state and to preserve a coherence property of stored quantum states to a fidelity level. A fidelity system is coupled to the quantum store and configured to identify if the quantum state that has a coherence property that is not at the fidelity level using monitoring that preserves a coherence property of quantum states to the fidelity level. The fidelity system is further configure to generate classical data about the quantum state if the coherence property is not at the fidelity level, wherein the generated classical data comprises an index associated with the quantum state. Classical data is generated about the quantum state and is transmitted over a classical channel, thereby informing an application that the quantum state having the associated index has the coherence property that is not at the fidelity level.

Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing pins of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided through the pins of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.

Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.

A new device executing an application on a new central processing unit (CPU), determines whether the application is for a legacy device having a legacy CPU. When the new device determines that the application is for the legacy device, it executes the application on the new CPU with selected available resources of the new device restricted to approximate or match a processing behavior of the legacy CPU, e.g., by reducing a usable portion of a return address stack of the new CPU and thereby reducing a number of calls and associated returns that can be tracked

A network-on-package (NoPK) for connecting a plurality of chiplets may include a plurality of interface bridges configured to convert a plurality of protocols used by the plurality of chiplets into a common protocol, a routing network configured to route traffic between the plurality of interface bridges using the common protocol, and a controller configured to program the plurality of interface bridges and the routing network based on types of the plurality of chiplets connected to the NoPK. The NoPK may provide a scalable connection for any number of chiplets from different ecosystems using different communication protocols.

The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the control method includes the steps of : receiving a settling command from a host device to configure a portion space of the flash memory module as a zoned namespace; receiving a write command from the host device to write data corresponding a first zone into a plurality of blocks of the flash memory module, wherein an access mode chose by the flash memory controller is determined based on a size of each zone and a size of each block.