Disclosed herein are methods, apparatuses and systems related to adjusting operation of memory dies according to reliability measures determined in real-time. The apparatus may be configured to determine the reliability measures based on (1) initiating and completing a programming operation within respective timings following an erase operation and (2) reading the programmed data within a window from completing the programming operation.

A system, method and apparatus to facilitate data exchange via pointers. For example, in a computing system having a first processor and a second processor that is separate and independent from the first processor, the first processor can run a program configured to use a pointer identifying a virtual memory address having an ID of an object and an offset within the object. The first processor can use the virtual memory address to store data at a memory location in the computing system and/or identify a routine at the memory location for execution by the second processor. After the pointer is communicated from the first processor to the second processor, the second processor can access the same memory location identified by the virtual memory address. The second processor may operate on the data stored at the memory location or load the routine from the memory location for execution.

A memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.

A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.

A method can include storing first instruction data in a first region of a nonvolatile memory device; mapping addresses of the first region to predetermined memory address spaces of a processor device; executing the first instruction data from the first region with the processor device; receiving second instruction data for the processor device. While the first instruction data remains available to the processor device, the second instruction data can be written into a second region of the nonvolatile memory device. By operation of the processor device, addresses of the second region can be remapped to the predetermined memory address spaces of the processor device; and executing the second instruction data from the second region with the processor device.

A memory system includes a memory medium and a memory controller. The memory medium has a second address system that is different from a first address system of a host. The memory controller performs a control operation to access the memory medium based on a command from the host. The memory controller is configured to store a second address, corresponding to an address of a read data, when an error of the read data that is outputted from the memory medium is uncorrectable and is configured to repair a region of the memory medium, designated by the second address, when the region of the memory medium that is designated by the second address is repairable.

Asynchronous completion notification is provided in a data processing system including one or more cores each executing one or more threads. A hardware unit of the data processing system receives and enqueues a request for processing and a source tag indicating at least a thread and core that issued the request. The hardware unit maintains a pointer to a completion area in a memory space. The completion area includes a completion granule for the hardware unit and thread. The hardware unit performs the processing requested by the request and computes an address of the completion granule based on the pointer and the source tag. The hardware unit then provides completion notification for the request by updating the completion granule with a value indicating a completion status.

Various embodiments of a distributed numeric sequence generation system and method are described. In particular, some embodiments provide high-scale, high-availability, low-cost and low-maintenance numeric sequence generation in a non-Relational Database Management System (“non-RBMS”) system by sacrificing monotonicity. The distributed numeric sequence generation system comprises a plurality of hosts, wherein individual hosts implement a cache for caching a plurality of numeric sequences. A host can access master numeric sequence data at a separate system to obtain values for numeric sequences to store in its cache. A host can receive a request from a client for values of a numeric sequence, and provide to the client the values for the numeric sequence from its cache. Some embodiments of the distributed numeric sequence generation system and method are also equipped to vend recyclable and bounded numeric sequences.

A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.

A processor may implement position-independent memory addressing by providing load and store instructions that include position-independent addressing modes. A memory address may contain a normalized pointer, where the memory address stores a normalized memory address that, when added to an offset previously determined for memory address, defines another memory address. The position-independent addressing mode may also support invalid memory addresses using a reserved value, where a load instruction providing the position-independent addressing mode may return a NULL value or generate an exception when determining that the stored normalized memory address is equal to the reserved value and where a store instruction providing the position-independent addressing mode may store the reserved value when determining that the memory address is an invalid or NULL memory address.