Provided are a computer program product, system, and method for using track status information on active or inactive status of track to determine whether to process a host request on a fast access channel. A host request to access a target track is received on a first channel to the host. A determination is made as to whether the target track has active or inactive status. The target track has active status when at least one process currently maintains a lock on the target track that prevents access and the target track has inactive status when no process maintains a lock on the target track that prevents access. Fail is returned to the host to cause the host to resend the host request on a second channel in response to the target track having the active status. The first channel has lower latency than the second channel.

A network device performs packet processing operations on packets received from a network and includes a write back cache to store data (for example, counters) used to perform the packet processing operations. The data stored in the write cache in the network device are evicted from the write back cache to an external memory from time to time using a write-back operation that includes a read-modify-write of a line in the external memory. Instead of performing a separate read-modify-write for each data stored in the cache line, a single read-modify-write operation is performed for all data stored in the cache line in the write back cache. The aggregation of relatively close data for the single read-modify-write operation reduces the number of memory accesses to the external memory and improves the bandwidth to the external memory.

Disclosed embodiments relate to adjusting vehicle Electronic Control Unit (ECU) software versions. Operations may include receiving a prompt to adjust an ECU of a vehicle from executing a first version of ECU software to a second version of ECU software; configuring, in response to the prompt and based on a delta file corresponding to the second version of ECU software, the second version of ECU software on the ECU in the vehicle for execution; and configuring, in response to the prompt, the first version of ECU software on the ECU in the vehicle to become non-executable.

The present disclosure may include a processor that uses idle caches as a backing store for a boot code. The processor designates a boot core and an active cache from a plurality of cores and a plurality of caches. The processor configures remaining caches from the plurality of caches to act as a backing store memory. The processor modifies the active cache to convert cast outs to a system memory into lateral cast outs to the backing store memory. The processor copies a boot image to the backing store memory and executes the boot image by the boot core.

A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.

A method, computer program product, and computing system for assigning a plurality of unique sequential identifiers to a plurality of tablets in a cache memory system. One or more metadata deltas associated with a metadata page stored in a storage array may be written to the plurality of tablets in the cache memory system. Each metadata delta stored in at least one tablet of the plurality of tablets may be written to the metadata page stored in the storage array, thus defining one or more destage tablets. A largest unique sequential identifier from the plurality of unique sequential identifiers assigned to the one or more destage tablets, may be written to the storage array, thus defining a current tablet identifier for the metadata page.

Aspects of the present disclosure relate to an apparatus comprising prefetch information storage circuitry and prefetch training circuitry. The prefetch training circuitry comprises a plurality of entries, and is configured to: allocate a given entry to a given data address region; receive access information indicative of data accesses within the given data address region; based on said access information, train prefetch information associated with the given data address region, the prefetch information being indicative of a pattern of said data accesses within the given data address region; and responsive to an eviction condition being met after an elapsed period, since said allocation of the given entry, has exceeded a threshold, perform an eviction comprising transferring the prefetch information associated with the given data address region to the prefetch information storage circuitry.

Disclosed embodiments relate to identifying Electronic Control Unit (ECU) anomalies in a vehicle. Operations may include monitoring, in the vehicle, data representing real-time processing activity of the ECU; accessing, in the vehicle, historical data relating to processing activity of the ECU, the historical data representing expected processing activity of the ECU; comparing, in the vehicle, the real-time processing activity data with the historical data, to identify at least one anomaly in the real-time processing activity of the ECU; and implementing a control action for the ECU when the at least one anomaly is identified.

An access control method for a shared memory includes: creating and initializing the shared memory, the shared memory initialized including a plurality of region configuration objects, a plurality of block configuration objects and a plurality of data buffers; determining at least one target block according to a volume of data to be written corresponding to a first process; and writing the data by the first process into a target data buffer corresponding to the at least one target block, storing configuration information of the at least one target block to a region configuration object corresponding to a target region, and storing configuration information of the target data buffer to a block configuration object corresponding to the at least one target block.

Methods and systems for validating cache coherence in a data processing system are described. A processing element may detect a load instruction requesting the processing element to transfer data from a global memory location to a local memory location. The processing element may apply, in response to detecting the load instruction requesting the processing element to transfer data from the global memory location to the local memory location, a delay to the transfer of the data from the global memory location to the local memory location. The processing element may execute the load instruction and transferring the data from the global memory location to the local memory location with the applied delay. The processing element may validate, in response to executing the load instruction and transferring the data with the applied delay, a cache coherence of the data processing system.