A computer system includes a first group of CPU modules operatively coupled to at least one first Programmable ASIC Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second Programmable ASIC Node Controller connected to a second group of CPU modules running a single instance of an operating system.

A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that receives a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one of a plurality of virtual memory pools to produce a mapping result, and providing the mapping result to the processor.

The present disclosure includes apparatuses and methods for compute enabled cache. An example apparatus comprises a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.

A method and system for providing memory in a computer system. The method includes receiving a memory access request for a shared memory address from a processor, mapping the received memory access request to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.

Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks The plurality of memory banks are configured to he arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

Examples of the present disclosure provide apparatuses and methods related to a translation lookaside buffer in memory. An example method comprises receiving a command including a virtual address from a host translating the virtual address to a physical address on volatile memory of a memory device using a translation lookaside buffer (TLB).

The present disclosure includes apparatuses and methods for compute enabled cache. An example apparatus comprises a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.

This invention relates to computer engineering and operating system components, in particular, it discloses a new method of building a hierarchal file system, which provides new functionality and flexibility, including: unlimited maximum possible file system size (number of elements), unlimited size of a single element, unlimited types of data, that can be represented as a file. In addition, the disclosed file system allows for user-defined types of data and can be used as a registry for OS system components, saving space important for resource-restricted embedded systems. The minimum file system size is 2 Bytes only. File system supports empty or non-unique files naming and natively provides built-in security using specification-based nodes header encoding.

This result is achieved by using file systems nodes metadata comprising: the unique identifier (ID), an ASN.1 header with PER encoding, and a doubly linked list of logical blocks of its data. ID is of Unlimited Integer type and consist of 2 parts: preamble (extension bit) and Integer number. Nodes of a special types, for example, system nodes or nodes with new types defined by the developers of OS or related file system manager component, can utilize a special delegated processing. When reading and decoding a header of a node of a non-standard type, the file manager or utilities delegate processing of the node to a custom component that knows how to process this type of node.

The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.

Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.