A data prefetching method and apparatus, and related storage device are provided. Data samples are collected. An AI chip trains the data samples to obtain a prefetching model. The AI chip then sends the prefetching model to a processor. The processor reads to-be-read data into a cache based on the prefetching model to reduce the computing burden of the processor.

Techniques are disclosed relating to address mapping for message signaled interrupts. In some embodiments, an apparatus includes interrupt control circuitry configured to process, from multiple client circuits, message signaled interrupts that include addresses in an interrupt controller address space. First and second interface controller circuitry may control respective peripheral interfaces for multiple devices. Remap control circuitry may be configured to access a first table based on at least a portion of virtual addresses of a first message signaled interrupt from the first interface controller circuit and generate a first address in the interrupt controller address space based on an accessed entry in the first table and access a second table based on at least a portion of virtual addresses of a second message signaled interrupt from the second interface controller circuit and generate a second address in the interrupt controller address space based on an accessed entry in the second table.

A mapping table management method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a read command from a host system, wherein the read command indicates reading a first data stored in at least one first logical address; and searching whether a relation management information reflects that a first group static mapping table recording the first logical address is related to a dynamic mapping table. In response to a search result reflecting that the first group static mapping table is related to the dynamic mapping table, the dynamic mapping table is searched to obtain a first physical address mapped by the first logical address. And if not related, the first group static mapping table among group static mapping tables is searched to obtain a second physical address mapped by the first logical address.

A cache system includes a cache memory having a plurality of blocks, a dirty line list storing status information of a predetermined number of dirty lines among dirty lines in the plurality of blocks, and a cache controller controlling a data caching operation of the cache memory and providing statuses and variation of statuses of the dirty lines, according to the data caching operation, to the dirty line list. The cache controller performs a control operation to always store status information of a least-recently-used (LRU) dirty line into a predetermined storage location of the dirty line list.

Client devices associated with scale-out storage nodes can be managed based on scale-out storage nodes having backup power supplies. For example, a management node of a scale-out storage system can determine, from among a plurality of storage nodes of the scale-out system, that a first storage node is uncoupled to a backup power supply and that a second storage node is coupled to the backup power supply. The management node can receive device characteristics describing a type of workload and a configuration for a client device associated with the first storage node. The management node can determine the client device satisfies a migration policy based on the device characteristics. The management node can migrate the client device to the second storage node based on the client device satisfying the migration policy.

The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the control method includes the steps of: receiving a settling command from a host device to configure a portion space of the flash memory module as a zoned namespace; receiving a write command from the host device to write data corresponding a first zone into a plurality of blocks of the flash memory module, wherein an access mode chose by the flash memory controller is determined based on a size of each zone and a size of each block.

In response to receiving a read request for target data, an external address of the target data is obtained from the read request, which is an address unmapped to a storage system; hit information of the target data in cache of the storage system is determined based on the external address; and based on the hit information, an address from the external address and an internal address for providing the target data is determined. The internal address is determined based on the external address and a mapping relationship. Therefore, it can shorten the data access path, accelerate the responding speed for the data access request, and allow the cache to prefetch the data more efficiently.

A method of operating a data storage device includes programming non-fully programmed memory blocks at a point in time when a reference time elapses from a point in time when each of the memory blocks is physically erased, acquiring a first interval and a second interval, calculating a disturb index based on the first interval and the second interval, selecting a victim block for garbage collection based on the disturb index, and copying valid page data of the victim block into a free block. The first interval is defined by a point in time when each of the memory blocks is physically erased and a point in time when each of the memory blocks is fully programmed. The second interval is an interval during which a fully programmed state is maintained after a point in time when each of the memory blocks is fully programmed.

A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache.

A method and system for efficiently executing a delegate of a program by a processor coupled to an external memory. A payload including state data or command data is bound with a program delegate. The payload is mapped with the delegate via the payload identifier. The payload is pushed to a repository buffer in the external memory. The payload is flushed by reading the payload identifier and loading the payload from the repository buffer. The delegate is executed using the loaded payload.