A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, architectures are introduced for the compression of the soft bit data to reduce the amount of data transferred over the memory's input-output interface. For a memory device with multiple planes of memory cells, the internal global data bus is segmented and a data compression circuit associated with each segment. This allows soft bit data from a cache buffer of a plane using one segment to transfer data between the cache buffer and the associated compression circuit concurrently with transferring data from a cache buffer of another plane using another segment, either for compression or transfer to the input-output interface.

Methods, systems, and devices for cache architectures for memory devices are described. For example, a memory device may include a main array having a first set of memory cells, a cache having a second set of memory cells, and a cache delay register configured to store an indication of cache addresses associated with recently performed access operations. In some examples, the cache delay register may be operated as a first-in-first-out (FIFO) register of cache addresses, where a cache address associated with a performed access operation may be added to the beginning of the FIFO register, and a cache address at the end of the FIFO register may be purged. Information associated with access operations on the main array may be maintained in the cache, and accessed directly (e.g., without another accessing of the main array), at least as long as the cache address is present in the cache delay register.

A processing device is provided which includes memory comprising data cache memory configured to store compressed data and metadata cache memory configured to store metadata, each portion of metadata comprising an encoding used to compress a portion of data. The processing device also includes at least one processor configured to compress portions of data and select, based on one or more utility level metrics, portions of metadata to be stored in the metadata cache memory. The at least one processor is also configured to store, in the metadata cache memory, the portions of metadata selected to be stored in the metadata cache memory, store, in the data cache memory, each portion of compressed data having a selected portion of corresponding metadata stored in the metadata cache memory. Each portion of compressed data, having the selected portion of corresponding metadata stored in the metadata cache memory, is decompressed.

A method includes determining respective memory access counts of a plurality of blocks of non-volatile memory cells that are grouped into a plurality of respective groups, comparing the respective memory access counts to respective memory access thresholds, determining a respective memory access count of a block of non-volatile memory cells exceeds a respective memory access threshold, and performing a media scan operation on the block of non-volatile memory cells.

A computing system can include an off-chip memory and processing unit integrated circuitry. The processing unit IC can include on-chip compute circuitry, a first on-chip memory and a second on-chip memory. The off-chip memory can be configured to store instructions and data The first on-chip memory can be configured to store reusable portions of the instructions and or data for use by the on-chip compute circuitry. The second on-chip memory configured to cache portions of instruction and data for current use by the on-chip compute circuitry.

For each data in a plurality of data, data is read from a cache unit. For each data in the plurality of data, a group to which the data read from the cache unit belongs to is determined based at least in part on a predetermined grouping rule. A determination is made of (1) a quantity of groups and (2) a quantity of data corresponding to each group after determining the groups to which the plurality of data belong. Data belonging to a same group is written into a contiguous storage space of the cache unit, including by: sequentially reading the plurality of data from the cache unit and sequentially writing the plurality of data into the cache unit.

A method is described. The method includes constructing a bitmap having a first dimension organized into bins of logical block addresses (LBA bins) and a second dimension organized into bins of physical block addresses (PBA bins). Coordinates of the bitmap indicate whether respective physical blocks of non volatile memory within one or more SSDs that fall within a particular PBA bin are being mapped to by an LBA that falls within a particular one of the LBA bins. The method includes using the bitmap during a rebuild of an LBA bin of an LBA/PBA table to avoid reading meta data for physical blocks that are not mapped to by an LBA that falls within the LBA bin.

An electronic device capable of accessing a memory and a data writing method are provided. The electronic device includes a processing unit, a bus, and a memory controller. The processing unit includes a bus interface control circuit, and the processing unit generates a first write command through the bus interface control circuit according to a memory access command. The memory access command contains a first memory address and a target value, and the first write command contains the first memory address and the target value. The bus is coupled to the bus interface control circuit and configured to generate a second write command according to the first write command. The second write command contains a second memory address and the target value. The memory controller is coupled to the bus and configured to write the target value into the memory according to the second memory address.

A networked system includes a computing device having a central processing system and accelerator system(s). A central processor/accelerator power management system coupled to the computing device via a network operates to deploy workload(s) on the computing device and receive workload performance information from the computing device that identifies a central processing system utilization of the central processing system in performing the workload(s) and an accelerator system utilization of each accelerator system in performing the workload(s). Based on the workload performance information, the computing device determines a first power consumption ratio of the central processing system and the accelerator system(s) in performing the workload(s), and modifies operation of at least one of the central processing system and the accelerator system(s) to change the first power consumption ratio to a second power consumption ratio that is more power efficient than the first power consumption ratio.