Systems and methods for memory management for nested virtual machines. An example method may comprise running, by a host computer system, a Level 0 hypervisor managing a Level 1 virtual machine running a Level 1 hypervisor, wherein the Level 1 hypervisor manages a Level 2 virtual machine, wherein the Level 2 virtual machine is associated with a Peripheral Component Interconnect (PCI) device; generating, by the Level 0 hypervisor, a Level 1 page table by combining records from the guest page table with records from a host page table maintained by the Level 0 hypervisor; generating a Level 2 page table comprising a plurality of Level 2 page table entries; and causing a device driver of the Level 2 virtual machine to use the Level 2 page table for second level address translation.

A cache and memory coherent system includes multiple processing chips each hosting a different subset of a shared memory space and one or more routing tables defining access routes between logical addresses of the shared memory space and endpoints that each correspond to a select one of the multiple processing chips. The system further includes a coherent mesh fabric that physically couples together each pair of the multiple processing chips, the coherent mesh fabric being configured to execute routing logic for updating the one or more routing tables responsive to identification of a first processing chip of the multiple processing chips hosting a defective hardware component, the update to the routing tables being effective to remove all access routes having endpoints corresponding to the first processing chip.

A method of error management includes, in response to a read request for first data from a first storage device of a plurality of storage devices under one or more common data protection schemes, receiving a read uncorrectable indication regarding the first data, obtaining uncorrected data and metadata of an LBA associated with the first data, and obtaining the same LBA from one or more other storage devices of the plurality. The method further includes comparing the uncorrected data with the data and metadata from the other storage devices, speculatively modifying the uncorrected data based, at least in part, on the other data to create a set of reconstructed first data codewords, and, in response to a determination that one of the reconstructed first data codewords has recovered the first data, issuing a write_raw command to rewrite the modified data and associated metadata to the first storage device.

A storage device includes a nonvolatile memory, a volatile memory, and a controller accesses the nonvolatile memory using an address conversion table including regions, each region including entries, each entry storing a physical address of the nonvolatile memory in association with a logical address, and reads and writes data of the address conversion table from and to the nonvolatile memory and the volatile memory in a unit of a frame. The controller writes, to the nonvolatile memory, data of a first region in a first format in which a head address of data of a region aligns with a head address of a frame, and writes, to the volatile memory, data of a second region in either the first format or a second format in which a head address of data of a region does not align with a head address of a frame.

A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.

A throttling engine throttles access to a high latency hybrid memory. A request is received for partition mapping of a virtual address for an R/W memory page. An entry is added to a partition page table that maps a virtual address to a physical address and comprises access information that is R/W. A throttled flag is set in an entry of a partition page extension table. The throttle entry corresponds to the entry. The access information is saved in an original access part of the partition page extension table, and the access information is replaced with an R value. Upon application fault receipt, a throttling test is performed on an address of the application fault. If the throttling test is false, the fault is passed through to an operating system fault handler and the throttling fault stage is ended, otherwise, a delay is implemented for slowing access to the memory.

A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

A storage device includes a nonvolatile memory including a plurality of first blocks having memory cells each configured to store one bit of data and a plurality of second blocks having memory cells each configured to multiple bits of data; and a controller configured to determine whether or not a number of use-completed second blocks, each of which has a first threshold number or less of valid pages, among use-completed second blocks of the plurality of second blocks, is equal to or larger than a second threshold number and to select, according to a determination result, a victim block on which garbage collection is to be performed among used-completed first blocks of the plurality of first blocks or the use-completed second blocks each having the first threshold number or less of valid pages.

Various embodiments of a distributed numeric sequence generation system and method are described. In particular, some embodiments provide high-scale, high-availability, low-cost and low-maintenance numeric sequence generation in a non-Relational Database Management System (“non-RBMS”) system by sacrificing monotonicity. The distributed numeric sequence generation system comprises a plurality of hosts, wherein individual hosts implement a cache for caching a plurality of numeric sequences. A host can access master numeric sequence data at a separate system to obtain values for numeric sequences to store in its cache. A host can receive a request from a client for values of a numeric sequence, and provide to the client the values for the numeric sequence from its cache. Some embodiments of the distributed numeric sequence generation system and method are also equipped to vend recyclable and bounded numeric sequences.

A request to perform a read operation on a memory device is received. The memory device includes a first group of memory cells. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The read operation is performed by obtaining a first read signal for a first memory cell and a second read signal for a second memory cell of the first group of memory cells. A first rule logic is applied to the first read signal to generate a first updated signal and a second rule logic is applied to the second read signal to generate a second updated signal. Logic functions are applied to the first and second updated signals to generate an output signal indicating the first sequence of bits stored by the first group of memory cells.