A method includes saving a control state for a processor in response to commencing a transactional processing sequence, wherein saving the control state produces a saved control state. The method also includes permitting updates to the control state for the processor while executing the transactional processing sequence. Examples of updates to the control state include key mask changes, primary region table origin changes, primary segment table origin changes, CPU tracing mode changes, and interrupt mode changes. The method also includes restoring the control state for the processor to the saved control state in response to encountering a transactional error during the transactional processing sequence. In some embodiments, saving the control state comprises saving the current control state to memory corresponding to internal registers for an unused thread or another level of virtualization. A corresponding computer system and computer program product are also disclosed herein.

A data storage device utilized for storing a plurality of data includes a memory and a controller. The memory includes a plurality of blocks, and each of the blocks includes a plurality of physical pages. The controller is coupled to the memory and maps the logical pages to the physical pages of the memory. When the controller detects that a first logical page of the logical pages is a currently-used logical page, it detects whether or not the second logical page which belongs to the last logical page of the first logical page is a currently-used logical page in order to find what is truly the last currently-used logical page.

An integrated circuit includes a functional core configured to execute functional logic instructions; a functional memory device coupled to the functional core; a safety core configured to execute safety check logic instructions; a monitored address memory device coupled to the functional core and the safety core, the monitored address memory device configured to store memory addresses to be monitored; and a first safety memory device coupled to the functional memory device and the safety core. When a value in one of the monitored memory addresses changes, the changed value of the one of the monitored memory addresses is stored in the functional memory device and in the first safety memory device. The safety core performs a safety check on the changed value of the one of the monitored memory addresses stored in the first safety memory device.

A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.

The present disclosure relates to a system and method for optimizing switching of a DRAM bus using LLC. An embodiment of the disclosure includes sending a first type request from a first type queue to the second memory via the memory bus if a direction setting of the memory bus is in a first direction corresponding to the first type request, decrementing a current direction credit count by a first type transaction decrement value, if the decremented current direction credit count is greater than zero, sending another first type request to the second memory via the memory bus and decrementing the current direction credit count again by the first type transaction decrement value, and if the decremented current direction credit count is zero, switching the direction setting of the memory bus to a second direction and resetting the current direction credit count to a second type initial value.

An integrated circuit (IC) is provided. The IC includes a cache memory divided into a plurality of groups and an address decoder. The groups are assigned in rotation for a plurality of time periods. Each group is assigned in a corresponding single one of the time periods. The address decoder is configured to obtain a set address according to an access address and provide a physical address according to the set address. When the access address corresponds to a first group, the physical address is different from the set address. When the access address corresponds to the groups other than the first group, the physical address is the same as the set address. The sets of the first group that is assigned in a first time period are not overlapping with the sets of other first groups assigned in the time periods other than the first time period.

A cache memory having a memory media device row activation-biased caching policy is described. The cache policies that are biased based on row activation counts include at least one of a cache line eviction policy which determines which cache lines are the most evictable from the cache memory, and cache line storage policy which determined which row data is allocated cache lines for storage. A memory controller including a row activation-biased cache memory is also described. The memory media device may be DRAM.

A system comprising a row hammer mitigation circuitry and a cache memory that collaborate to mitigate row hammer attacks on a memory media device is described. The cache memory biases cache policy based on row access count information maintained by the row hammer mitigation circuit. The row hammer mitigation circuitry may be implemented in a memory controller. The memory media device may be DRAM. Corresponding methods are also described.

A controller controls a memory device. The controller includes a buffer buffering one or more data chunks received from a host until the one or more data chunk is stored in the memory device, and a processor sorting and storing, according to data types of the one or more data chunks, the one or more data chunks buffered in the buffer in a plurality of memory regions of the memory device in a normal operation, the plurality of memory regions respectively corresponding to a plurality of data types. In response to a sudden power-off (SPO), the processor generates map data indicating a relationship between the one or more data chunks and the plurality of memory regions, generates a data string by merging the one or more data chunks, and stores the data string and the map data in a temporal memory region of the memory device.

A method may include storing at least a portion of a metadata buffer of a persistent data structure in volatile memory, and storing at least a portion of a data buffer of the persistent data structure in persistent memory. A system may include a processor, a volatile memory coupled to the processor, and a persistent memory coupled to the processor. The processor may be configured to execute procedures including storing at least a portion of a metadata buffer of a persistent data structure in volatile memory, and storing at least a portion of a data buffer of the persistent data structure in persistent memory. A method may include storing at least a portion of a transient part of a persistent data structure in volatile memory, and storing at least a portion of a persistent part of the persistent data structure in persistent memory.