Aspects are provided for sharing instruction cache footprint between multiple threads using instruction cache set/way pointers and a tracking table. The tracking table is built up over time for shared pages, even when the instruction cache has no access to real addresses or translation information. A set/way pointer to an instruction cache line is derived from the system memory address associated with a first thread's instruction fetch. The set/way pointer is stored as a surrogate for the system memory address in both an instruction cache directory (IDIR) and a tracking table. Another set/way pointer to an instruction cache line is derived from the system memory address associated with a second thread's instruction fetch. A match is detected between the set/way pointer and the other set/way pointer. The instruction cache directory is updated to indicate that the instruction cache line is shared between multiple threads.

In a method, an instance management node receives a request for creating a service instance; the instance management node obtains a cache configuration corresponding to the service instance; and the instance management node creates the service instance on a computing node, and creates a cache instance on the computing node based on the cache configuration. In this way, the service instance may provide a service by using the matched cache instance.

Techniques for manipulation of a recursive neural network using random access memory are disclosed. Neural network descriptor information and weight matrices are stored in a semiconductor random access memory device which includes neural network processing logic. The network descriptor information and weight matrices comprise a trained neural network functionality. An input matrix is obtained for processing on the memory device. The trained neural network functionality is executed on the input matrix, which includes processing data for a first layer from the neural network descriptor information to set up the processing logic; manipulating the input matrix using the processing logic and at least one of the weight matrices; caching results of the manipulating in a storage location of the memory device; and processing recursively the results that were cached through the processing logic. Additional data for additional layers is processed until the neural network functionality is complete.

A list of a first type of tracks in a cache is generated. A list of a second type of tracks in the cache is generated, wherein I/O operations are completed relatively faster to the first type of tracks than to the second type of tracks. A determination is made as to whether to demote a track from the list of the first type of tracks or from the list of the second type of tracks.

Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.

A method to store a data value onto a cache of a storage hierarchy. A range of a collection of values that resides on a first tier of the hierarchy is initialized. The range is partitioned into disjointed range partitions; a first subset of which is designated as cached; a second subset is designated as uncached. The collection is partitioned into a subset of uncached data and cached data and placed into respective partions. The range partition to which the data value belongs (i.e. the target range partition) is identified as being cached. If the cache is full all cached range partitions that do not contain the data value are designated as uncached. All values that lie in the cached range partitions designated as uncached are evicted. The data value is then inserted into the target range partition, and copied to the first tier.

Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to manage the memory device using a cell level assignment with respect to a plurality of memory cell levels, determine a cell count for each of the cell levels associated with original data of the memory device that is to be accessed, predict an error rate from the cell counts, and selectively adjust the cell level assignment based on the error rate.

Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.

A novel design for conflict free address generation mechanism is provided for reading data from Block RAM (BRAM) into a Fast Fourier Transform (FFT) module and writing back the processed data back to the BRAM. Also, a novel way of reducing a memory footprint by reducing a twiddle factor table size by taking an advantage of the symmetry property of twiddle factors is presented. Further, additional architecture-specific optimizations are provided, which involve a design of deeply pipelined butterfly modules and the BRAM accesses, parallel butterfly modules for a single FFT block and parallel FFT lane implementation.