A memory device includes: a plurality of memory cells grouped into a plurality of planes; page buffer groups corresponding to respective ones of the plurality of planes, the page buffer groups including a plurality of page buffer circuits, each of the plurality of page buffer circuits including cache latches which are configured to receive data to be stored in memory cells in the plurality of planes; and control logic for controlling the page buffer groups to simultaneously initialize cache latches corresponding to at least two planes, among the cache latches, in response to a multi-plane program command, wherein the multi-plane program command instructs a multi-plane program operation of simultaneously storing data in plural planes among the plurality of planes.

An access control method for a shared memory includes: creating and initializing the shared memory, the shared memory initialized including a plurality of region configuration objects, a plurality of block configuration objects and a plurality of data buffers; determining at least one target block according to a volume of data to be written corresponding to a first process; and writing the data by the first process into a target data buffer corresponding to the at least one target block, storing configuration information of the at least one target block to a region configuration object corresponding to a target region, and storing configuration information of the target data buffer to a block configuration object corresponding to the at least one target block.

A machine-implemented method for managing a flash storage system includes determining a projected life value for each of a plurality of flash memory devices in the flash storage system, wherein the projected life value for at least one of the plurality of flash memory devices is higher than the projected life value of at least another one of the plurality of flash memory devices. The method also includes determining operating parameters for each of the plurality of flash memory devices based on the respective projected life values for the plurality of flash memory devices. The method also includes configuring the plurality of flash memory devices based on the determined operating parameters.

According to at least one embodiment, a method for writing, by a computing thread, data to a ring buffer is disclosed. The method includes determining whether the ring buffer is full. If the ring buffer is not full, the method further includes: reserving an element of the ring buffer for writing the data, wherein reserving the element includes incrementing a size variable corresponding to a number of stored elements in the ring buffer; reserving a portion of the ring buffer at which the data is to be written; and determining whether a state of the portion of the ring buffer is in change by at least one other computing thread. If the state is not in change, the method further includes: marking the state of the portion of the ring buffer as being in change by the computing thread; and writing the data to the portion of the ring buffer.

Host data is written to a set of pages of a page stripe of a storage area of a memory sub-system. A set of exclusive or (XOR) parity values corresponding to the host data written to a portion of the set of pages of the storage area is generated. An additional XOR parity value is generated by executing an XOR operation using the set of XOR parity values. Parity data including the set of XOR parity values and the additional XOR parity value is stored in a cache memory of the memory sub-system. The parity data is written to an available page stripe of the storage area.

One example method includes determining a modulus such as a Weibull modulus for a recovery operation. Enablement and disablement of a read ahead cache are performed based on the modulus. The modulus is a linearization of a cumulative distribution function, where failures correspond to non-sequential accesses and successes correspond to sequential accesses.

Methods, systems, and devices for access control configurations for inter-processor communications are described to support reconfiguration of a dynamic access control configuration at a device. For example, additional configuration fields may be added to existing access control rules of the device, where these additional fields may be configured by a processor sending information to a receiving processor, via a shared memory resource or region of the device. The additional fields may include a read-only value which may specify a processor which has exclusive write permission for a memory region of the share memory. This value may indicate the sending processor of the memory region, and the value may be set by access control hardware when the additional field is changed. Other processors of the device may be prevented from writing to the memory region.

A solid state drive having a drive aggregator and multiple component solid state drives. Different component solid state drives in solid state drive are configured with different optimizations of memory/storage operations. An address map in the solid state drive is used by the drive aggregator to host different namespaces in the component solid state drives based on optimization requirements of the namespaces and based on the optimizations of memory operations that have been implement in the component solid state drives.

A server includes a data cache for storing data objects requested by mobile devices, desktop devices, and server devices, each of which may execute a different configuration of an application. When a cache miss occurs, the cache may begin loading portions of a requested data object from various data sources. The cache itself may be divided into multiple partitions, and each of the partitions may be assigned to a specific attribute, such as an application configuration. Portions of the data object may be loaded into corresponding cache partitions based on the attributes of each. Although part of a single cache, each of the partitions may be independently assigned different cache replacement policies. Performance metrics for each of the partitions may be monitored and used to update the cache replacement policy for each partition at runtime without interrupting response traffic.

A memory device is described, including a command decoder configured to receive a copy command to copy data stored in a first memory location to a second memory location without transmitting the data to an external controller, a memory array electrically connected to the command decoder and including a plurality of memory locations including the first memory location and the second memory location, a data line electrically connected to the memory array and configured to receive, from the first memory location, the data to be transmitted to the second memory location through the same data line, and an output buffer configured to store the data received from the first memory location through the data line to be written into the second memory location without transmitting the data to the external controller.