Systems, apparatuses and methods may provide for technology that generates address information for a plurality of planes in NAND memory, excludes column information from the address information, and sends a read command sequence to the NAND memory, wherein the read command sequence includes the address information. In one example, the technology also excludes plane confirm commands and busy cycles from the read command sequence.

Disclosed herein are system, apparatus, article of manufacture, method, and/or computer program product embodiments for providing rolling updates of distributed systems with a shared cache. An embodiment operates by receiving a platform update request to update data item information associated with a first version of a data item cached in a shared cache memory. The embodiment may further operate by transmitting a cache update request to update the data item information of the first version of the data item cached in the shared cache memory, and isolating the first version of the data item cached in the shared cache memory based on a collection of version specific identifiers and a version agnostic identifier associated with the data item.

A method for writing to a non-volatile electronic memory with data words and assigned pieces of index information. The non-volatile electronic memory is initially filled exclusively with empty data frames. The empty data frames are overwritable with multi-data frames and/or individual data frames. A multi-data frame includes a selectable number of sequentially stored data words, and a multi-data frame header. A frame-type marker, the number of data words, and a selectable start index are stored in the multi-data frame header so that each data word is assignable a unique index value from an index interval by incrementing or decrementing. An individual data frame includes one data word and an individual data frame header. A frame-type marker and a selectable index value for the one data word of the individual data frame are stored in the individual data frame header.

A virtual disk is provided to a computing environment. The virtual disk includes identity information to enable identification of a virtual machine within the computing environment. A size of the virtual disk is increased within the computing environment to enable the virtual disk to act as a storage for the identity information and as a cache of other system data to operate the virtual machine. The virtual machine is booted within the computing environment. The virtual machine is configured to at least access the virtual disk that includes both identity information and caches other system data to operate the virtual machine. Related apparatus, systems, techniques and articles are also described.

A method for extending a blockchain comprises, at a space server: allocating an amount of drive storage for generating proofs-of-space; or accessing a first challenge based on a prior block of the blockchain, the prior block comprising a first proof-of-space and a first proof-of-time; in response to accessing the first challenge, generating a second proof-of-space based on the first challenge and the amount of drive storage, the second proof-of-space indicating allocation of the amount of drive storage; accessing a second proof-of-time based on the prior block and indicating a first time delay elapsed after extension of the blockchain with the prior block; generating a new block comprising the second proof-of-space and the second proof-of-time; and broadcasting the new block over a distributed network.

The present disclosure advantageously provides a hybrid memory artificial neural network hardware accelerator that includes a communication bus interface, a static memory, a non-refreshed dynamic memory, a controller and a computing engine. The static memory stores at least a portion of an ANN model. The ANN model includes an input layer, one or more hidden layers and an output layer, ANN basis weights, input data and output data. The non-refreshed dynamic memory is configured to store ANN custom weights for the input, hidden and output layers, and output data. For each layer or layer portion, the computing engine generates the ANN custom weights based on the ANN basis weights, stores the ANN custom weights in the non-refreshed dynamic memory, executes the layer or layer portion, based on inputs and the ANN custom weights, to generate layer output data, and stores the layer output data.

A cache storage system indexing method is provided that indexes a data address in a cache storage system based on a data fingerprint of the cached data, wherein the data fingerprint is generated by a deduplication fingerprint function used for referencing deduplication of data in the cache storage system. A computer-implemented method of data operations to a cache storage system is also provided including: obtaining a data fingerprint for the data of the data operation, either by applying a deduplication fingerprinting function to data of a write operation or by accessing deduplication metadata for a read operation to obtain the data fingerprint generated by using a deduplication fingerprinting function used for deduplication of data in the cache storage system; and using an indexing service to the cache storage system having an address schema based on the data fingerprints of the data.

Devices and techniques for managing hazards in a memory controller are described herein. The memory controller can receive a memory request that includes a base memory address. An index can be computed from the base memory address and a lookup, using the index, can be performed to find a lock. When the lock is found, the memory controller can store the memory request in a buffer that corresponds to the lock. In response to a signal to clear the lock, the memory controller removes the memory request from the buffer and performs the memory request.

A method of operating a storage device with a memory includes partitioning an entire area of a first namespace into at least one area based on a reference size. The partitioning is performed in response to a namespace creating request from a host that includes size information corresponding to the entire area of the first namespace. The method further includes partitioning a logical address space of the memory into a plurality of segments, allocating a first segment of the plurality of segments to a first area of the at least one area, and storing mapping information of the first area and the first segment. A size of the logical address space is greater than a size of a physical storage space of the memory identified by the host.

A mechanism is described for facilitating optimization of cache associated with graphics processors at computing devices. A method of embodiments, as described herein, includes introducing coloring bits to contents of a cache associated with a processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes.