The disclosed computer-implemented method may include (1) receiving, at a storage device via a cache-coherent interconnect, a first request to access data at one or more host addresses of a coherent memory space of an external host processor, (2) updating, in response to the first request, one or more statistics associated with accessing the data at the one or more host addresses, (3) receiving, at the storage device via the cache-coherent interconnect, a second request to perform an operation associated with the one or more statistics, and (4) using the one or more statistics to perform the operation. Various other methods, systems, and computer-readable media are also disclosed.

Embodiments are disclosed for recycling memory after a virtual machine reboots. Memory allocated to a rebooting virtual machine instance can be associated with the instance or otherwise marked as to be reserved for use after the virtual machine instance reboots. Subsequently, after the reboot process is initiated, the reserved memory can be reallocated to the virtual machine instance. Memory scrubbing can be ordinarily performed to avoid data leakage between customers, but scrubbing can be inhibited for memory that is returned to a rebooting virtual machine instance. Further features, such as API calls to configure memory recycling, indications to disable recycling, and the like can be supported.

A memory disposition device of a computer system in which a plurality of nodes exists, each of the nodes including a pair of a processor and a memory, the memory disposition device includes: at least one memory configured to store instructions; and at least one processor configured to execute the instructions to: determine a node in which a memory area to be mapped is disposed; and duplicate the memory area and disposing the memory area, based on a determination result, in a local memory of a node in which a process operates, wherein the at least one processor is configured to invalidate maintenance of cache coherency between the nodes and invalidates access to a remote memory for the process.

A request for data from a cache (TLB or data/instruction cache) specifies a partition identifier allocated to a software execution environment associated with the request. Allocation of data to the cache is controlled based on a set of configuration information selected based on the partition identifier specified by the request. For a TLB, this allows different allocation policies to be used for requests associated with different software execution environments. In one example, the cache allocation is controlled based on an allocation threshold specified by the selected set of configuration information, which limits the maximum number of cache entries allowed to be allocated with data associated with the corresponding partition identifier.

The disclosure herein provides systems, methods, and computer program products for managing a plurality of operands in a computer instruction. To manage the plurality of operands, a data buffer manager executed by a processor receives information from a caller. The information relates to the plurality of operands. The data buffer manager, also, compares a free data area size to a requested minimum data area of an operand size identified by the information; selects an address when the requested minimum data area is less than or equal to the free data area size; and inserts the operand at the address.

A data system may dynamically prioritize and ingest data so that, regardless of the memory size of the dataset hosted by the data system, it may process and analyze the hosted dataset in constant time. The system and method may implement a first space-efficient probabilistic data structure on the dataset, wherein the dataset includes a plurality of profile data. It may then receive update data corresponding to some of the plurality of profile data and implement a second space-efficient probabilistic data structure on the dataset including the update data. The system and method may then determine a set of non-shared profile data of the second space-efficient probabilistic data structure and prioritize the set of non-shared profile data of the second space-efficient probabilistic data structure over other profile data of the dataset for caching.

The present disclosure includes apparatuses, systems, and methods related to multiple address registers for a solid state device (SSD). An example apparatus includes a controller including a plurality of base address registers (BARs) each including same addresses for data storage in a same memory resource and an SSD that includes the same memory resource.

An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to carry concurrent write requests to the memory unit for a write operation, wherein the first write request is always presented by its write interface directly to a crossbar, wherein the rest of the write requests are each fed through a set of temporary memory modules connected in a sequence before being presented to the crossbar. The crossbar is configured to accept the first write request directly and fetch the rest of the write requests from one of the memory modules in the set and route each of the write requests to one of the memory banks in the memory unit.

A memory subsystem package is provided that has processing logic for data reorganization within the memory subsystem package. The processing logic is adapted to reorganize data stored within the memory subsystem package. In some embodiments, the memory subsystem package includes memory units, a memory interconnect, and a data reorganization engine (“DRE”). The data reorganization engine includes a stream interconnect and DRE units including a control processor and a load-store unit. The control processor is adapted to execute instructions to control a data reorganization. The load-store unit is adapted to process data move commands received from the control processor via the stream interconnect for loading data from a load memory address of a memory unit and storing data to a store memory address of a memory unit.

A computing system that uses a Scale-Out NUMA (“soNUMA”) architecture, programming model, and/or communication protocol provides for low-latency, distributed in-memory processing. Using soNUMA, a programming model is layered directly on top of a NUMA memory fabric via a stateless messaging protocol. To facilitate interactions between the application, OS, and the fabric, soNUMA uses a remote memory controller—an architecturally-exposed hardware block integrated into the node's local coherence hierarchy.